Editing socionext/sc2a11

{{socionext title|SC2A11}}
{{mpu
| future              = Yes
| name                = Socionext SC2A11
| no image            = 
| image               = SC2A11 IMG01.jpg
| image size          = 
| caption             = 
| designer            = Socionext
| designer 2          = ARM Holdings
| manufacturer        = 
| model number        = SC2A11
| part number         = 
| part number 1       = 
| part number 2       = 
| part number 3       = 
| market              = Server
| market 2            = Networking
| market 3            = IoT
| first announced     = November 14, 2016
| first launched      = 2017
| last order          = 
| last shipment       = 
| release price       = 

| family              = 
| series              = 
| locked              = 
| frequency           = 1,000 MHz
| bus type            = AMBA
| bus speed           = <!-- (Property::bus speed) -->
| bus rate            = <!-- (Property::bus rate) -->
| bus links           = <!-- ?x bus rate -->
| clock multiplier    = 

| isa family          = ARM
| isa                 = ARMv8
| microarch           = Cortex-A53
| platform            = 
| chipset             = 
| core name           = Cortex-A53
| core family         = 
| core model          = 
| core stepping       = 
| transistors         = 
| technology          = CMOS
| die area            = <!-- XX mm² -->
| die width           = 
| die length          = 
| word size           = 64 bit
| core count          = 24
| thread count        = 24
| max cpus            = 
| max memory          = 

| electrical          = <!-- put Yes if electrical info is added -->
| power               = <!-- power consumption  -->
| v core              = 
| v core tolerance    = 
| v io                = 
| v io tolerance      = 
| v io 2              = <!-- OR ... -->
| v io 3              = 
| sdp                 = 
| tdp                 = 
| tdp typical         = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = <!-- use TJ/TC whenever possible instead -->
| temp max            = 
| tjunc min           = <!-- .. °C -->
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 
| tambient min        = 
| tambient max        = 

| package module 1    = 
| package module 2    = 

| packaging           = <!-- put Yes if packaging info is added -->
| package 0           = 
| package 0 type      = 
| package 0 pins      = 
| package 0 pitch     = 
| package 0 width     = 
| package 0 length    = 
| package 0 height    = 
| socket 0            = 
| socket 0 type       = 
}}
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.


{{unknown features}}
== Cache ==
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
{{cache size
|l1 cache = 1.5 MiB
|l1i cache=768 KiB
|l1i break=24x32 KiB
|l1i desc=2-way set associative
|l1d cache=768 KiB
|l1d break=24x32 KiB
|l1d desc=4-way set associative
|l2 cache=1.5 MiB
|l2 break=2x256 KiB
|l2 desc=16-way set associative
|l3 cache=4 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR4-2133
|ecc=Yes
|max mem=
|controllers=
|channels=1
|max bandwidth=15.89 GiB/s
|bandwidth schan=15.89 GiB/s
|bandwidth dchan=
}}

== Expansions ==
{{expansions
|pcie revision=2.0
|pcie lanes=4
|uart=4
|gp io=Yes
}}

== Graphics ==
This SoC has no integrated graphics processing unit.

== Networking ==
* 2x Gigabit Ethernet Interfaces

== Storage ==
* SPI
* eMMC
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	SC2A11 - Socionext#io +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
bus type	AMBA +
core count	24 +
core name	Cortex-A53 +
designer	Socionext + and ARM Holdings +
first announced	November 14, 2016 +
first launched	2017 +
full page name	socionext/sc2a11 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	4-way set associative +
l1d$ size	768 KiB (786,432 B, 0.75 MiB) +
l1i$ description	2-way set associative +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ description	16-way set associative +
l2$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	3000 +
main image	+
market segment	Server +, Networking + and IoT +
max cpu count	64 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	4 +
microarchitecture	Cortex-A53 +
model number	SC2A11 +
name	Socionext SC2A11 +
smp max ways	64 +
supported memory type	DDR4-2133 +
tdp	5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technology	CMOS +
thread count	24 +
word size	64 bit (8 octets, 16 nibbles) +