Editing cmu/piperench

{{cmu title|PipeRench}}
{{mpu
| name                = PipeRench
| image               = cmu piperench logo.gif
| image size          = 
| caption             = Logo
| designer            = Carnegie Mellon University
| manufacturer        = 
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| market              = 
| first announced     = April, 2000
| first launched      = 2002
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| family              = 
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| frequency           = 120 MHz
| bus type            = 
| bus speed           = 60 MHz
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| clock multiplier    = 2

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| process             = 180 nm
| transistors         = 3,650,000
| technology          = CMOS
| die size            = 49 mm²
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| electrical          = 
| power               = 4 W
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'''PipeRench''' was a research [[microprocessor]] designed at [[Carnegie Mellon University]] in the early 2000s. PipeRench was developed with a reconfigurable pipeline. This allows what would otherwise have to be implemented as specialized embedded chips to be implemented in a more generic way using PipeRench through reconfiguration.

Technology developed for this project was eventually leased to [[Rapport]] for their {{rapport|Kilocore}} architecture which eventually resulted in the {{rapport|KC256}}, a 256-core chip.

== Architecture ==
PipeRench is designed as a reconfigurable fabric. The chip breaks down each of its pipeline stages into individual ''stripes''. Each strip has a set of simple execution units (EU/PE), register files, and a interconnection network. By configuring each of the stripes using the interconnect network, it's possible to virtualize different kind of custom hardware. The ALU, for example contains additional circuitry to facilitate [[bit-slice microprocessor|bit-slicing]].

== Die Shot ==
[[File:cmu piperench die.jpg|450px]]

== Documents == 
* Seth C. Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matt Moe, and R. Reed Taylor, "[http://repository.cmu.edu/cgi/viewcontent.cgi?article=1792&context=compsci PipeRench: A Reconfigurable Architecture and Compiler]", April 2000, Carnegie Mellon University Computer Science Department.

== External links ==
* [https://www.ece.cmu.edu/research/piperench/ Official Website]
base frequency	120 MHz (0.12 GHz, 120,000 kHz) +
bus speed	60 MHz (0.06 GHz, 60,000 kHz) +
clock multiplier	2 +
designer	Carnegie Mellon University +
die area	49 mm² (0.076 in², 0.49 cm², 49,000,000 µm²) +
first announced	April 2000 +
first launched	2002 +
full page name	cmu/piperench +
instance of	microprocessor +
ldate	2002 +
main image	+
main image caption	Logo +
name	PipeRench +
power dissipation	4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process	180 nm (0.18 μm, 1.8e-4 mm) +
technology	CMOS +
transistor count	3,650,000 +