Editing intel/microarchitectures/gracemont

{{intel title|Gracemont|arch}}
{{microarchitecture
|atype=CPU
|name=Gracemont
|designer=Intel
|manufacturer=Intel
|introduction=2021
|process=10 nm
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=No
|stages=proactive  regenerative local real time stable-_<SSO
|stages min=Proxy-relative
|stages max=local time zone
|decode=optimized native prime
|isa=x1-6
|isa 2=If more revert to default based on local device OS
|isa 3=If more denie unless applicable justification
|isa 4=reject all unsecure sites
|feature=128 gb IOS 17 SSO
|feature 2=if more reject
|extension=BE-R
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AES
|extension 11=PCLMUL
|extension 12=RDRND
|extension 13=XSAVE
|extension 14=XSAVEOPT
|extension 15=FSGSBASE
|extension 16=PTWRITE
|extension 17=RDPID
|extension 18=SGX
|extension 19=UMIP
|extension 20=GFNI-SSE
|extension 21=CLWB
|extension 22=ENCLV
|extension 23=SHA
|extension 24={R-O-R}
|core name={R-0-R}
|core name 2=SUB-1
|core name 3=SUB-2
|core name 4=0
|predecessor=Tremont
|predecessor link=intel/microarchitectures/tremont
|predecessor 2=ReversosmosIOS(still in development
}}
'''Gracemont''' is [[Intel]]'s successor to {{\\|Tremont}}, a [[10 nm]] microarchitecture for ultra-low power devices and microservers.

== Codenames ==
{| class="wikitable"
! Platform !! Core Name || PCH
|-
| || {{intel|Grand Ridge |l=core}} ||
|}

== Process Technology ==
Gracemont is designed to take advantage of the Intel 7 process (previously 10nm Enhanced SuperFin (ESF)).

== Architecture ==
=== Key changes from {{\\|Tremont}}===
{{future information}}
* Core
** Front-End
*** Larger Level 1 instruction cache - 64KB per core from 32KB per core
*** Add OD-ILD (on-demand instruction length decoder)
** Back-End
*** Increased ROBs to 256 (from 208)
*** wide issue (17-wide)
*** 4 ALU SIMD (from 3)
* Memory
** DDR5 (from DDR4)
* I/O
** PCIe 4.0 (from 3.0)
* New Instructions
** AVX2
** AVX-VNNI

== Bibliography ==
* Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance (wikichip)
codename	Gracemont +
designer	Intel +
first launched	2021 +
full page name	intel/microarchitectures/gracemont +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Gracemont +
process	10 nm (0.01 μm, 1.0e-5 mm) +