Editing amd/ryzen 3/3200u

{{amd title|Ryzen 3 3200U}}
{{chip
|name=Ryzen 3 3200U
|no image=Yes
|designer=AMD
|manufacturer=GlobalFoundries
|model number=3200U
|part number=YM3200C4T2OFG
|market=Mobile
|first announced=January 6, 2019
|first launched=January 6, 2019
|family=Ryzen 3
|series=3000
|locked=Yes
|frequency=2,600 MHz
|turbo frequency=3,500 MHz
|bus type=PCIe 3.0
|clock multiplier=26
|isa=x86-64
|isa family=x86
|microarch=Zen+
|core name=Picasso
|process=12 nm
|transistors=4,940,000,000
|technology=CMOS
|die area=209.78 mm²
|word size=64 bit
|core count=2
|thread count=4
|max cpus=1
|max memory=64 GiB
|tdp=15 W
|tdp typical=15
|ctdp down=12 W
|ctdp up=35 W
|temp min=0° C
|temp max=105 °C
|package name 1=amd,socket_fp5
}}
'''Ryzen 3 3200U''' is a {{arch|64}} [[dual-core]] entry-level performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3200U operates at a base frequency of 2.6 GHz with a [[TDP]] of 15 W and a {{amd|Precision Boost|Boost}} frequency of 3.5 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 3}} Graphics operating at up to 1.2 GHz.

This model supports a configurable TDP-down of 12 W and TDP-up of 35 W.

== Cache ==
{{main|amd/microarchitectures/zen+#Memory_Hierarchy|l1=Zen+ § Cache}}
{{cache size
|l1 cache=192 KiB
|l1i cache=128 KiB
|l1i break=2x64 KiB
|l1i desc=4-way set associative
|l1d cache=64 KiB
|l1d break=2x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=1 MiB
|l2 break=2x512 KiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=4 MiB
|l3 break=1x4 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR4-2400
|ecc=Yes
|max mem=32 GiB
|controllers=2
|channels=2
|max bandwidth=35.76 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
}}

== Expansions ==
This processor has 12 PCIe lanes, 1x8 typically designated for a [[GPU]] and 4 additional lanes for storage (e.g., NVMe).
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=12
|pcie config=1x8+1x4
|pcie config 2=2x4+1x4
|pcie config 3=1x8+2x2
}}
}}

== Graphics ==
{{integrated graphics
| gpu                 = Radeon Vega 3
| device id           = 
| designer            = AMD
| execution units     = 3
| unified shaders     = 192
| max displays        = 3
| max memory          = 
| frequency           = 
| max frequency       = 1,200 MHz

| output crt          = 
| output sdvo         = 
| output dsi          = 
| output edp          = 
| output dp           = Yes
| output hdmi         = Yes
| output vga          = 
| output dvi          = 

| directx ver        = 12
| opengl ver         = 4.6
| opencl ver         = 2.2
| hdmi ver           = 
| dp ver             = 
| edp ver            = 
| max res hdmi       = 
| max res hdmi freq  = 
| max res dp         = 
| max res dp freq    = 
| max res edp        = 
| max res edp freq   = 
| max res vga        = 
| max res vga freq   = 
}}
{{zen with vega hardware accelerated video table|col=1}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=Yes
|avx=Yes
|avx2=Yes
|avx512f=No
|avx512cd=No
|avx512er=No
|avx512pf=No
|avx512bw=No
|avx512dq=No
|avx512vl=No
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=Yes
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=No
|tbmt3=No
|bpt=No
|eist=No
|sst=No
|flex=No
|fastmem=No
|ivmd=No
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=No
|txt=No
|ht=No
|vpro=No
|vtx=No
|vtd=No
|ept=No
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|intqat=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=Yes
|amdv=Yes
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=Yes
|sensemi=Yes
|xfr=No
|mxfr=No
|amdpb=No
|amdpb2=No
}}

== Die ==
{{further|amd/microarchitectures/zen+#Die|l1=Zen+ § Die}}
* [[14 nm process]]
* 4,940,000,000 transistors
* 209.78 mm² die size


: [[File:raven ridge die.png|650px]]


: [[File:raven ridge die (annotated).png|650px]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Ryzen 3 3200U - AMD#pcie +
base frequency	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
bus type	PCIe 3.0 +
clock multiplier	26 +
core count	2 +
core name	Picasso +
designer	AMD +
die area	209.78 mm² (0.325 in², 2.098 cm², 209,780,000 µm²) +
family	Ryzen 3 +
first announced	January 6, 2019 +
first launched	January 6, 2019 +
full page name	amd/ryzen 3/3200u +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd sensemi technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	Radeon Vega 3 +
integrated gpu designer	AMD +
integrated gpu execution units	3 +
integrated gpu max frequency	1,200 MHz (1.2 GHz, 1,200,000 KHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	192 KiB (196,608 B, 0.188 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	January 6, 2019 +
manufacturer	GlobalFoundries +
market segment	Mobile +
max cpu count	1 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max operating temperature	105 °C +
microarchitecture	Zen+ +
min operating temperature	0° C +
model number	3200U +
name	Ryzen 3 3200U +
package	FP5 +
part number	YM3200C4T2OFG +
process	12 nm (0.012 μm, 1.2e-5 mm) +
series	3000 +
smp max ways	1 +
supported memory type	DDR4-2400 +
tdp	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
tdp (typical)	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
tdp down	12 W (12,000 mW, 0.0161 hp, 0.012 kW) +
tdp up	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	4 +
transistor count	4,940,000,000 +
turbo frequency	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +