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- 08:47, 18 February 2020 (diff | hist) . . (+121) . . intel/microarchitectures/skylake (client) (→CPU changes: Remove points that aren't differences. https://uops.info/ shows MOVZX and MOVSX performance is identical between HSW and SKL for all combinations of operand size and reg or mem src. HSW ADC is p0156+p06 (except with imm=0), BDW p06)
- 08:30, 18 February 2020 (diff | hist) . . (+110) . . intel/microarchitectures/skylake (client) (→CPU changes: It's still only zeroing idioms at 4/clock; vPCMPGTx is new, not the vPCMPEQx all-ones idiom. (As before, it's dep-breaking but still needs p01; 2/clock))
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