Semiconductor & Computer Engineering
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Information for "renesas/r-car/h1"
Basic information
| Display title | R-Car H1 - Renesas |
| Default sort key | R-Car H1, Intel |
| Page length (in bytes) | 3,453 |
| Page ID | 21272 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 6 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | BCD (talk | contribs) |
| Date of page creation | 21:09, 20 July 2017 |
| Latest editor | ChippyBot (talk | contribs) |
| Date of latest edit | 16:32, 13 December 2017 |
| Total number of edits | 24 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (19) | Templates used on this page:
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Facts about "R-Car H1 - Renesas"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car H1 - Renesas#package + and R-Car H1 - Renesas#io + |
| base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + and 1,000 MHz (1 GHz, 1,000,000 kHz) + |
| core count | 5 + |
| core name | Cortex-A9 + and SH-4A + |
| core voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
| designer | Renesas + and ARM Holdings + |
| family | R-Car + |
| first announced | October 21, 2011 + |
| first launched | November 2011 + |
| full page name | renesas/r-car/h1 + |
| has ecc memory support | false + |
| instance of | microprocessor + |
| integrated gpu | PowerVR SGX543 + |
| integrated gpu base frequency | 250 MHz (0.25 GHz, 250,000 KHz) + |
| integrated gpu designer | Imagination Technologies + |
| integrated gpu execution units | 2 + |
| io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| isa | ARMv7 + |
| isa family | ARM + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | November 2011 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max cpu count | 1 + |
| max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
| max memory bandwidth | 7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 1 + |
| microarchitecture | Cortex-A9 + and SH-4A + |
| model number | H1 + |
| name | R-Car H1 + |
| package | FCBGA-832 + |
| part number | R8A77790 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) + |
| series | 1st Gen + |
| smp max ways | 1 + |
| supported memory type | DDR3-1066 + |
| technology | CMOS + |
| thread count | 5 + |
| word size | 32 bit (4 octets, 8 nibbles) + |
