Editing amd/packages/sp4

{{amd title|Package SP4}}
{{package
|name=SP4
|designer=AMD
|market=Embedded
|first launched=February 21, 2018
|microarch=Zen
|tdp=55 W
|tdp 2=100 W
|package name=SP4
|package type=FC-OBGA
|package contacts=
|package dimension=45 mm
|package dimension 2=45 mm
|package pitch=0.8 mm
}}
'''SP4''' and '''SP4r2''' are microprocessor packages of [[AMD]] {{amd|epyc embedded#3000 Series (Zen)|EPYC 3000}} "{{amd|Snowy Owl|l=core}}" embedded processors. Server processors of the same generation ({{amd|EPYC#7001 Series (Zen)|EPYC 7001}}) use {{\\|Socket SP3}}.

== Overview ==
SP4 and SP4r2 are [[ball grid array]] packages with 0.8&nbsp;mm non-uniform pitch,<!--AMD-54945-3.00-NDA Sec 1.8.5 & 1.8.6--> 45&nbsp;mm × 45&nbsp;mm in size,<!--ibid.--> with [[flip chip]] die attachment and a stiffener frame. The processors using these packages are members of AMD's x86 CPU {{amd|CPUID#Family 23 (17h)|Family 17h}} with CPU cores based on the {{amd|Zen|l=arch}} microarchitecture, and are fabricated on a [[GlobalFoundries]] [[14 nm#GlobalFoundries|14&nbsp;nm]] process.

SP4 is a [[multi-chip package]] with two identical "Zeppelin" ZP-B2<!--AMD-55449-1.19--> dies. AMD used the same dies in various revisions for EPYC 7001 server and embedded processors, first generation Ryzen Threadripper {{abbr|HEDT}} and Ryzen desktop processors; see {{amd|CPUID#Family 23 (17h)|CPU Family 17h}}. The pin compatible<!--AMD-1887102-E--> SP4r2 package carries one of these dies. They integrate eight CPU cores, two memory controllers, two 16-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so {{abbr|xGMI}} links are not supported. As on {{amd|Ryzen Threadripper#1900-Series (Zen)|Ryzen Threadripper 1900}} processors two {{abbr|GMI}} links connect the dies of the SP4 package.<!--AMD-54945-3.00-NDA Sec 1.8.5.3 & Tbl 162--> The multi-function I/O interfaces can be configured as PCIe, SATA, SATA Express,<!--AMD-54945--> or XGBE<!--ibid.--> links. The latter support the [[wikipedia:10 Gigabit Ethernet#Backplane|10GBASE-KR]], [[wikipedia:Gigabit Ethernet#1000BASE-KX|1000BASE-KX]], and [[wikipedia:Media-independent interface#Serial gigabit media-independent interface|SGMII]] (10/100/1000 Mbit/s) backplane Ethernet protocols.

== Features ==
* Lidless [[ball grid array]] package with stiffener frame, 45&nbsp;mm × 45&nbsp;mm
** ? contacts, 0.8&nbsp;mm non-uniform pitch
** Organic substrate, [[flip chip]] die attachment

* 4 × 72 bit DDR4 SDRAM interface (SP4)
* 2 × 72 bit DDR4 SDRAM interface (SP4r2)
** Up to 1333 MHz, PC4-21333 (DDR4-2666), 85.33 GB/s total raw bandwidth (SP4)
** Up to 2 DIMMs/channel
** {{abbr|SR}}/{{abbr|DR}} {{abbr|UDIMM}}, SR/DR {{abbr|SODIMM}}, SR/DR {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}, {{abbr|NVDIMM-N}} types
** ECC support
** Memory addressing up to ? GiB/channel
** Max. total memory capacity 1 TiB using 8 × 128 GiB LRDIMMs (SP4)

* Four multi-function I/O interfaces P0, P1, G0, G1 (SP4)
* Two multi-function I/O interfaces P0, G0 (SP4r2)
:{| class="wikitable" style="text-align:center"
|Lane||15||14||13||12||11||10||9||8||7||6||5||4||3||2||1||0
|-
|rowspan="5"|PCIe||colspan="16"|x16
|-
|colspan="8"|x8||colspan="8"|x8
|-
|colspan="4"|x4||colspan="4"|x4||colspan="4"|x4||colspan="4"|x4
|-
|colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2
|-
|x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1
|-
|SATAe||colspan="12"| ||colspan="2"|1||colspan="2"|0
|-
|SATA||colspan="8"| ||7||6||5||4||3||2||1||0
|-
|XGBE||colspan="8"| ||3||2||1||0||colspan="4"|
|-
| ||colspan="4"|PHY 4||colspan="4"|PHY 3||colspan="4"|PHY 2||colspan="2"|PHY 1||colspan="2"|PHY 0
|}
:* PCIe Gen 1, 2, 3 (8 GT/s) protocol supported on all interfaces
:** 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
:** Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
:** Max. 7 PCIe ports per interface if any lane is configured as SATA port
:** Different PCIe generations supported on the ports in the same interface
:** Lane polarity inversion, per port lane reversal
:** Up to 64 (SP4) or 32 (SP4r2) PCIe lanes total

:* SATA Express supported on the lowest four lanes of P0 and G1
:** Combines PCIe and SATA controllers on the same two lanes with a {{abbr|GPIO}} pin for a device to indicate its controller type
:** P0: SATAE00, SATAE01; G1: SATAE10, SATAE11
:** Up to 4 (SP4) or 2 (SP4r2) ports total

:* SATA Gen 1, 2, 3 (6 Gb/s) protocol supported on the lower 8 lanes of P0 and G1
:** P0: SATA00-07, G1: SATA10-17
:** Up to 16 (SP4) or 8 (SP4r2) ports total

:* XGBE protocols supported on lanes 4-7 of P0 and G1
:** P0: XGBE00-03, G1: XGBE10-13
:** Up to 8 (SP4) or 4 (SP4r2) ports total

:* Five {{abbr|PHY}} groups on each interface
:** Lanes sharing a PHY group must use the same protocol (PCIe, SATA, XGBE)

* 4 × USB 1.1, 2.0, 3.1 Gen 1 (5 Gb/s) ports

* Low speed interfaces: {{abbr|eMMC}}, {{abbr|UART}}, {{abbr|LPC}}, {{abbr|SPI/eSPI}}, {{abbr|I<sup>2</sup>C}}, {{abbr|SMBus}}, {{abbr|GPIO}} 

== Processors using package SP4/SP4r2 ==
<!-- NOTE:
This table is generated automatically from the data in the actual articles.
If a microprocessor is missing from the list, an appropriate article for it needs to be
created and tagged accordingly.
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable">
{{comp table header|cols|Cores|Threads|L2$|L3$|Base<br/>Frequ.|Turbo<br/>one core|Memory<br/>({{abbr|1DPC}})|Memory<br/>channels|T<sub>jmin</sub>|T<sub>jmax</sub>|{{abbr|cTDP}}↓|{{abbr|TDP}}|Package|Launched|Price|{{abbr|LTB}}|{{abbr|OPN}}}}
{{#ask: [[Category:microprocessor models by amd]] [[package::SP4||SP4r2]]
|?full page name
|?model number
|?core count
|?thread count
|?l2$ size
|?l3$ size
|?base frequency#GHz
|?turbo frequency (1 core)#GHz
|?supported memory type
|?max memory channels
|?min junction temperature#°C
|?max junction temperature#°C
|?tdp down
|?tdp
|?package
|?first launched
|?release price
|?last order
|?part number
|sort=model number
|format=template
|template=proc table 3
|userparam=19
|mainlabel=-
|valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[package::SP4||SP4r2]]}}
</table>
{{comp table end}}

== Photos ==
{{empty section}}

== Package Diagrams ==
{| style="text-align: center;"
|[[file:SP4 diag.svg]]<br/>SP4 package
|&nbsp;
|[[file:SP4r2 diag.svg]]<br/>SP4r2 package
|}

== Pin Map ==
{{empty section}}

== Bibliography ==
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|file=3000-Family-Product-Brief.pdf|publ=AMD|pid=1887102|date=2018}}
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|url=https://www.amd.com/system/files/documents/updated-3000-family-product-brief.pdf|publ=AMD|pid=1887102|rev=E|date=2019}}
* {{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|url=https://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf|publ=AMD|pid=54945|rev=1.14|date=2017-04-15}}
* {{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publ=AMD|pid=54945|rev=3.00|date=2019-04-14}}
* {{cite techdoc|title=Revision Guide for AMD Family 17h Models 00h-0Fh Processors|publ=AMD|pid=55449|rev=1.19|date=2019-12}}
* [https://www.amd.com/en/products/specifications/embedded "Embedded Processor Specifications"]. AMD.com.

== See also ==
* {{\\|Socket SP3}}
* {{\\|Socket TR4}}

[[Category:amd]]
designer	AMD +
first launched	February 21, 2018 +
instance of	package +
market segment	Embedded +
microarchitecture	Zen +
name	SP4 +
package	SP4 +
package length	45 mm (4.5 cm, 1.772 in) +
package pitch	0.8 mm (0.0315 in) +
package type	FC-OBGA +
package width	45 mm (4.5 cm, 1.772 in) +
tdp	100 W (100,000 mW, 0.134 hp, 0.1 kW) +