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[[File:arm3 cache.svg|right|500px]] | [[File:arm3 cache.svg|right|500px]] | ||
− | The ARM3's cache consists of a RAM and 4 tag [[CAM]] banks of 64 22-bit entries each for 64-way set associative. The choice of a 4-way split was entirely driven by the great reduction in power dissipation ( | + | The ARM3's cache consists of a RAM and 4 tag [[CAM]] banks of 64 22-bit entries each for 64-way set associative. The choice of a 4-way split was entirely driven by the great reduction in power dissipation, at the cost of negligible performance (due to only 1/4th of the total CAM being enabled at any given time). Each CAM entry refers to one line of data in the RAM. Each line consists of four 32-bit words (i.e., 128 bit lines) with the low-order address bits being used for the select lines. |
On a miss, a [[pseudo-random number generator]] is used to select an entry to evict and replace. On replacement a full line of four words is fetched from memory to minimize consecutive read operations. The cache uses a write-through update policy to ensure consistency. On a hit the appropriate line address are generated to be retrieved by the RAM. | On a miss, a [[pseudo-random number generator]] is used to select an entry to evict and replace. On replacement a full line of four words is fetched from memory to minimize consecutive read operations. The cache uses a write-through update policy to ensure consistency. On a hit the appropriate line address are generated to be retrieved by the RAM. |
Facts about "ARM3 - Microarchitectures - Acorn"
codename | ARM3 + |
core count | 1 + |
designer | Acorn Computers + |
first launched | 1989 + |
full page name | acorn/microarchitectures/arm3 + |
instance of | microarchitecture + |
instruction set architecture | ARMv2a + |
manufacturer | VLSI Technology + and Sanyo + |
microarchitecture type | CPU + |
name | ARM3 + |
pipeline stages | 3 + |
process | 1,500 nm (1.5 μm, 0.0015 mm) + |