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Saphira - Microarchitectures - Qualcomm
Edit Values | |
Saphira µarch | |
General Info | |
Arch Type | CPU |
Designer | Qualcomm |
Manufacturer | Samsung |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 10-15 |
Decode | 4-way |
Instructions | |
ISA | ARMv8.4 |
Extensions | Hypervisor (EL2), TrustZone (EL3), NEON, CRC32, Crypto, FP, RDM |
Cache | |
L1I Cache | 64 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 512 KiB/duplex 8-way set associative |
L3 Cache | 5 MiB/block 20-way set associative |
Succession | |
Saphira is Qualcomm's successor to Falkor, an ARM microarchitecture for the server market.
Process Technology[edit]
Qualcomm has not yet disclosed the process chosen for Saphira but it will most likely be on Samsung's 8nm (DUV) or 7nm (EUV).
Release dates[edit]
Qualcomm first disclosed Saphira at the official launch of the Centriq server family on November 8, 2017.
Architecture[edit]
Key changes from Falkor[edit]
- ARMv8.3 (from ARMv8)
Facts about "Saphira - Microarchitectures - Qualcomm"
codename | Saphira + |
designer | Qualcomm + |
full page name | qualcomm/microarchitectures/saphira + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.4 + |
manufacturer | Samsung + |
microarchitecture type | CPU + |
name | Saphira + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 10 + |