Page title matches

• Property:has hardware accelerators for network quality of service processing
  ...integrated circuit has [[hardware accelerators]] for network [[quality of service]] processing.
  162 bytes (23 words) - 15:24, 10 December 2016

Page text matches

• mirc/sockets
  ...know|This article assumes that you have intermediate to advanced knowledge of the [[mIRC Scripting Language]] and familiarity with [[On events - mIRC|on '''mIRC Sockets''' are a set of {{mIRC|commands}}, {{mIRC|identifiers}}, and {{mIRC|on events|events}} that
  4 KB (740 words) - 09:43, 22 September 2017
• amd/microarchitectures/zen 2
  ...confirmed that Zen 2 was set to utilize [[7 nm process]]. Initial details of Zen 2 and {{amd|Rome|l=core}} were unveiled during AMD's Next Horizon event Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth a
  57 KB (8,701 words) - 22:11, 9 October 2022
• cavium/microarchitectures/cnmips
  ...d applications (L3 through L7) in mind which resulted in a large selection of hardware accelerators (compression/security) being included. ...ad of Cavium's CTO Richard Kessler (who was previously the chief architect of the {{decc|EV7}}). The fully custom final design proved to be around three
  7 KB (870 words) - 19:38, 23 June 2017
• cavium/octeon
  ...ed in mid-[[2005]]. These processors are primarily marketed towards makers of network infrastructure (commercial, enterprise, and data center switches, r ...EON family of network-oriented microprocessors were announced in September of [[2004]]. These chips are based on [[Cavium]]'s newly announced microarchit
  11 KB (1,489 words) - 09:25, 30 December 2020
• Property:has hardware accelerators for network quality of service processing
  ...integrated circuit has [[hardware accelerators]] for network [[quality of service]] processing.
  162 bytes (23 words) - 15:24, 10 December 2016
• cavium/octeon plus
  ...offering double the cache, double the clock speeds, and double the number of various acceleration units. ...cessors operate at twice the previous clock speeds and introduced a number of incremental improvements such as a larger cache.
  6 KB (827 words) - 15:41, 29 December 2016
• qualcomm/microarchitectures/falkor
  ...designed by Qualcomm from the ground up for the server market. While some of the core architecture ressmbles Qualcomm's mobile cores, the overall system ** [[Out-of-order]] Pipeline
  6 KB (822 words) - 13:01, 19 May 2021
• amd/microarchitectures/zen 3
  ...during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the {{\\|Zen}} microarchitecture. On Investor's Day in May 2017 Jim Anderso Note: Only the APU series of microprocessors retains the monolithic design, so they are fabricated solel
  15 KB (1,978 words) - 22:13, 6 April 2023
• cavium/octeon tx
  ...mily combines the features of the {{\\|OCTEON}} family with the technology of the {{\\|ThunderX}} processors. |?has hardware accelerators for network quality of service processing
  4 KB (483 words) - 18:35, 1 February 2019
• qualcomm/snapdragon 800/845
  ...pporting Cat 13 uplink and Cat 18 downlink. This chip supports up to 8 GiB of quad-channel LPDDR4X-3733 memory. * Slow motion HEVC video encoding of either HD (720p) video up to 480fps or FHD (1080p) up to 240fps
  7 KB (943 words) - 15:22, 17 June 2023
• habana/microarchitectures/gaudi
  Gaudi was designed as a microarchitecture for the [[acceleration]] of training in the data center. It is offered as a PCIe-based [[accelerator ca ...r to facilitate large scale-out capabilities, Gaudi integrates a large set of ethernet ports and [[high-bandwidth memory]].
  5 KB (662 words) - 18:36, 16 July 2020
• amd/List of AMD publications
  {{amd title|List of AMD publications}} |16294||A||White Paper: The Effect of Local Buffer Memory Size on FDDI Throughput||1992-01||
  181 KB (24,861 words) - 16:02, 17 April 2022