• intel/xeon d
  ...nd networking - areas where dense, lower-power, lightweight [[hyperscale]] workloads are expected.
  13 KB (1,784 words) - 08:04, 6 April 2019
• intel/microarchitectures/sandy bridge (client)
  ...er Control Unit. The cores and graphics scale up and down depending on the workloads in order to deliver instantaneous performance boost through higher frequenc ...decode pipeline instead. However, such scenarios are fairly rare and most workloads do benefit from this feature.
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...s that Skylake also succeeded in reducing power by 40-60% during important workloads such as video, graphics, and idle power which especially affect models wher ...power reduction - (mobile segment) The reduction of power during critical workloads such as video playback, video conferencing, and various other multimedia ap
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...ority of the package power budget allocated for the CPU to accelerate that workloads while things like gaming will shift the power in favor of GPU acceleration.
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/coffee lake
  ...increased the number of cores by 50% (later by 100%), enabling much higher multi-threaded performance. The enhanced manufacturing process should allow Coffee Lake ch * IPC improvement from larger cache for various workloads, but actual core is unchanged
  30 KB (4,192 words) - 13:48, 10 December 2023
• pezy/pezy-scx/pezy-sc2
  ...of deep learning and AI as well as to increase throughput for specialized workloads, the PEZY-SC2 introduced support for 16-bit half precision floating point s
  5 KB (683 words) - 11:15, 22 September 2018
• intel/microarchitectures/gen9.5
  ...D shaders, media, and [[GPGPU]] kernels. Internally, each unit is hardware multi-threaded capable of executing multi-issue [[SIMD]] operations. Execution is multi-is ...omplete kernel execution) to mid-thread (instruction boundary) for compute workloads:
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...D shaders, media, and [[GPGPU]] kernels. Internally, each unit is hardware multi-threaded capable of executing multi-issue [[SIMD]] operations. Execution is multi-is ...omplete kernel execution) to mid-thread (instruction boundary) for compute workloads:
  33 KB (4,255 words) - 17:41, 1 November 2018
• intel/xeon bronze
  ...ally positioned for price-sensitive applications which require light-range workloads with enhanced security features and large memory. Additionally, those proce ...6|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the bronze 3100-series microprocessors feature dual-socket capabili
  7 KB (973 words) - 14:08, 2 June 2019
• intel/xeon silver
  ...E5}}/{{intel|Xeon E7|E7}} families. Xeon Silver is geared toward mid-range workloads dual-socket server. Xeon Silver processors are a set above the {{intel|Xeon ...6|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the Silver 4100-series microprocessors feature dual-socket capabili
  7 KB (993 words) - 02:57, 2 March 2020
• intel/xeon gold
  ...6|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the gold 5100/6100-series microprocessors feature four-way [[SMP]]
  9 KB (1,195 words) - 05:38, 8 June 2021
• intel/xeon platinum
  ...6|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the platinum 8100-series microprocessors feature eight-way [[SMP]]
  11 KB (1,476 words) - 17:13, 30 December 2022
• amd/cores/milan
  ...eman, Martin. "Innovator Insights: AMD Epyc for High Performance Computing Workloads". [http://www.hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php H
  19 KB (2,734 words) - 01:26, 31 May 2021
• amdahl's law
  Amdahl's Law says that for fixed workloads, the upper bound of the speedup expected from moving to a more parallelized
  3 KB (485 words) - 16:58, 19 May 2019
• physical core
  ...e|little]]) cores. Depending on the workloads the microprocessor may shift workloads between the cores in order to deliver higher performance or high power effi
  2 KB (294 words) - 01:39, 13 June 2018
• apple/ax/a11
  ...and is said to offer up to 70% performance improvement in [[multi-threaded workloads]].
  4 KB (661 words) - 23:51, 3 January 2021
• intel/microarchitectures/cascade lake
  ...hich is designed to improve the performance of [[Artificial Intelligence]] workloads by improving the throughput of tight inner convolutional loop operations. ...f frquency (base, turbo, or otherwise) enable custom tuning of affinitized workloads.
  32 KB (4,535 words) - 05:44, 9 October 2022
• x86/tme
  ...ttestation mechanisms, or other key provisioning services. For virtualized workloads, a [[hypervisor]] can manage the keys to transparently provide memory encry
  6 KB (970 words) - 02:40, 17 December 2017
• nervana/microarchitectures/spring crest
  ...er efficiency. Emphasis was placed on the reuse of on-die data and batched workloads.
  11 KB (1,646 words) - 13:35, 26 April 2020
• zhaoxin/microarchitectures/wudaokou
  * 140% higher performance in multi-threaded workloads ...tecture to have 25% improvement in [[IPC]], 140% improvement in multi-core workloads, and 120% higher memory access bandwidth.
  9 KB (1,134 words) - 13:02, 17 June 2019

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