• list of microprocessor families
  Below is a '''list of [[microprocessor families]]''' organized by company, alphabetized. * [[list of instruction set architectures]]
  12 KB (1,182 words) - 12:35, 13 March 2022
• 4-bit architecture
  ...th]] width or a highest [[operand]] width of 4 bits or a [[nibble]]. These architectures typically have a matching [[register file]] with [[registers]] width of 4 b ...hift to larger architectures such as {{arch|8|8-}} and {{arch|12|12-}} bit architectures.
  4 KB (580 words) - 09:37, 12 December 2020
• immediate value
  ...[[MIPS32]], an immediate value is limited to 16-bits. On some more complex architectures such as [[ARM]], some instructions may accept a 16-bit value, others might [[Category:microprocessor architecture]]
  2 KB (387 words) - 09:09, 28 August 2020
• 1-bit architecture
  ...at has a [[datapath]] width or a highest [[operand]] width of 1 bit. These architectures typically have a matching [[register file]] with [[registers]] width of 1 b
  1 KB (191 words) - 14:45, 21 March 2024
• 8-bit architecture
  ...th]] width or a highest [[operand]] width of 8 bits or an [[octet]]. These architectures typically have a matching [[register file]] with [[registers]] width of 8 b As a departure from the older [[4-bit architecture|4-bit]] [[microprocessor]]s, 8-bit CPUs found their way to many military applications, scientific in
  2 KB (232 words) - 09:18, 24 June 2017
• 2-bit architecture
  ...2-bit architecture CPUs were commercially marketed, most were [[bit-slice microprocessor]]s.
  511 bytes (62 words) - 22:59, 16 January 2016
• 12-bit architecture
  ...] width or a highest [[operand]] width of 12 bits or 1.5 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 12
  679 bytes (83 words) - 13:36, 7 October 2016
• 16-bit architecture
  ...h]] width or a highest [[operand]] width of 16 bits or 2 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 16
  1 KB (135 words) - 12:16, 20 July 2018
• 20-bit architecture
  ...] width or a highest [[operand]] width of 20 bits or 2.5 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 20
  410 bytes (50 words) - 23:02, 16 January 2016
• microprocessor family
  ...ties, clock speeds, and applications. Models may be further divided into [[microprocessor stepping|stepping]] which are minor refinements and tweaks in order to corr On occasion, a manufacturer may decide to group a number of smaller microprocessor families into a larger '''extended family''' which represents a large group
  1 KB (193 words) - 02:07, 1 May 2017
• national semiconductor
  '''National Semiconductor''' is a [[semiconductor]] [[microprocessor|chip]] maker. On September 23, 2011, the company became part of [[Texas Ins == Instruction set architectures ==
  1 KB (114 words) - 05:19, 29 April 2016
• 24-bit architecture
  ...h]] width or a highest [[operand]] width of 24 bits or 3 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 24
  484 bytes (58 words) - 10:06, 28 May 2017
• 32-bit architecture
  ...operand]] width (i.e. natural word size) of 32 bits or 4 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 32
  1 KB (137 words) - 18:55, 5 December 2019
• 64-bit architecture
  ...h]] width or a highest [[operand]] width of 64 bits or 8 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 64
  2 KB (240 words) - 01:48, 17 March 2019
• 15-bit architecture
  ...has a [[datapath]] width or a highest [[operand]] width of 15 bits. These architectures typically have a matching [[register file]] with [[registers]] width of 15
  372 bytes (47 words) - 23:26, 16 January 2016
• 18-bit architecture
  ...has a [[datapath]] width or a highest [[operand]] width of 18 bits. These architectures typically have a matching [[register file]] with [[registers]] width of 18
  419 bytes (53 words) - 23:50, 16 January 2016
• 36-bit architecture
  ...has a [[datapath]] width or a highest [[operand]] width of 36 bits . These architectures typically have a matching [[register file]] with [[registers]] width of 36
  578 bytes (67 words) - 06:19, 27 June 2018
• intel/microarchitectures/bonnell
  ...was a [[microarchitecture]] for [[Intel]]'s [[45 nm]] ultra-low voltage [[microprocessor]]s first introduced in 2008 for their then-new {{intel|Atom}} family. Bonne ...scarding many high-performance techniques used by Intel's high-performance architectures such as aggressive [[speculative execution]], [[out-of-order]] execution, a
  38 KB (5,468 words) - 19:29, 23 May 2019
• intel/microarchitectures/sandy bridge (client)
  ...e-implemented and enhanced in Sandy Bridge. This is different from earlier architectures (i.e., {{\\|Core}} through {{\\|Nehalem}}) which were almost exclusively en ...s been set to 100 MHz. Note that this has changed from 133 MHz in previous architectures. The BCLK is the reference edge for all the clock domains. Because the core
  84 KB (13,075 words) - 23:54, 28 December 2020
• intel/microarchitectures/skylake (client)
  ...design philosophy which was enhanced significantly over the past number of architectures. Skylake, like its predecessor {{\\|Broadwell}}, is also a dual-threaded an ...ew proprietary [[DMI 3.0]] bus. The upgrade from DMI 2.0 (used in previous architectures) to 3.0 increased the bandwidth by 60% (8.0 GT/s from 5). For some models w
  79 KB (11,922 words) - 05:46, 11 November 2022

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)