• intel
  ...er [[integrated circuit]]s including [[flash memory]], [[network interface controller]]s, [[GPU]]s, [[chipset]]s, motherboards, and computers. * {{\\|Programmable Unified Memory Architecture}} (PUMA)
  9 KB (1,150 words) - 00:03, 2 October 2022
• national semiconductor/cops ii
  The '''COP400''' or '''COPS II''' or simply '''COPS''' ('''Controller Oriented Processor System II''') was a [[microprocessor family|family]] of ...rocontrollers, one of the earliest instances of multiple CPUs in on single integrated circuit.
  6 KB (685 words) - 22:49, 5 February 2016
• intel/core i7/i7-4950hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  4 KB (404 words) - 16:22, 13 December 2017
• intel/core i7/i7-4960hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (401 words) - 14:24, 12 February 2019
• intel/core i7/i7-4980hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}.
  3 KB (400 words) - 16:22, 13 December 2017
• intel/core i7/i7-4860hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4870hq
  |max memory=32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (386 words) - 09:14, 26 December 2017
• intel/core i7/i7-4750hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-4760hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (397 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (398 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770r
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  4 KB (406 words) - 16:22, 13 December 2017
• intel/core i5/i5-4670r
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  4 KB (404 words) - 16:19, 13 December 2017
• intel/core i5/i5-4570r
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (401 words) - 16:19, 13 December 2017
• intel/core i7/i7-4860eq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (396 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850eq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (391 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1284l v3
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (399 words) - 16:27, 13 December 2017
• intel/celeron/3855u
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  4 KB (596 words) - 16:15, 13 December 2017
• intel/celeron/3955u
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  4 KB (596 words) - 16:15, 13 December 2017
• intel/core i3/i3-6098p
  |max memory=64 GiB ...of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.
  4 KB (627 words) - 16:17, 13 December 2017

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