• intel/microarchitectures/haswell (client)
  * Platform Controller Hub (PCH) * New memory model for {{x86|TSX|Transactional Synchronization Extensions}}
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ** Memory Subsystem ** Dropped {{intel|QPI}} controller which linked the two dies
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ** Intel Sensor Solution Hub integration ** Memory Subsystem
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  * Memory ** Faster memory for mainstream desktops (i.e., {{intel|Kaby Lake S|l=core}}) DDR4-2400 (fro
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/core m
  Core M dies are packaged with the {{intel|Platform Controller Hub}} (PCH) die in the same packaging which is only about 1 mm thick and requir |?max memory#GB
  7 KB (949 words) - 20:01, 8 August 2018
• amd/microarchitectures/zen
  === Memory Hierarchy === ...n all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new [[SoC]] CCX (CPU Complex) modular design. T
  79 KB (12,095 words) - 15:27, 9 June 2023
• intel/cores/kaby lake s
  ...1}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake S|l=core}}) { * Dual-channel Memory
  5 KB (687 words) - 03:02, 11 October 2017
• intel/cores/kaby lake h
  ...0}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake H|l=core}}) { * Dual-channel Memory
  5 KB (699 words) - 13:43, 8 April 2018
• intel/cores/kaby lake x
  ...} and use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}). * Dual-channel Memory
  3 KB (443 words) - 10:07, 24 October 2018
• intel/cores/kaby lake dt
  ...1}} and use {{intel|Union Point}} chipset ({{intel|Platform Controller Hub|HUB}}) but they may also use previous generation ({{intel|Skylake DT|l=core}}) * Dual-channel Memory
  5 KB (660 words) - 08:08, 17 July 2018
• intel/cores/skylake sp
  ...s supporting hex-chanel 768 GiB of DDR4 ECC memory or 1.5 TiB for extended memory models. ...Those use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}) via 4 PCIe3 lanes using Intel's proprietary {{intel|Direct Media Interfa
  7 KB (934 words) - 14:21, 10 June 2018
• intel/cores/skylake s
  ...} and use {{intel|Sunrise Point}} chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory
  4 KB (619 words) - 04:05, 21 March 2019
• intel/cores/skylake x
  ...} and use the {{intel|Lewisburg}} chipset ({{intel|Platform Controller Hub|HUB}}). * Quad-channel Memory
  3 KB (470 words) - 10:12, 24 October 2018
• intel/cores/skylake dt
  ...} and use {{intel|Sunrise Point}} chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory
  4 KB (561 words) - 08:11, 17 July 2018
• intel/cores/skylake h
  ...} and use {{intel|Sunrise Point}} chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory
  5 KB (630 words) - 02:08, 16 January 2019
• amd/infinity fabric
  ...hooking together things such as [[PCIe]] PHYs, [[memory controller]]s, USB hub, and the various computing and execution units. The SDF is a [[superset]] o ...to the cores and to the other peripherals (e.g. memory controller and I/O hub) are routed through the SDF. A key feature of the coherent data fabric is t
  8 KB (1,271 words) - 21:50, 18 August 2020
• intel/cores/coffee lake s
  ...51}} and use {{intel|300-series}} chipset ({{intel|Platform Controller Hub|HUB}}). Despite using the same socket, those chips are not backwards-compatible * Dual-channel Memory
  4 KB (546 words) - 08:18, 1 January 2020
• intel/cores/coffee lake h
  ...440|BGA-1440}} and use 300-series chipset ({{intel|Platform Controller Hub|HUB}}). The microprocessor is connected to the chipset via 4 of the chip's 20 P * Dual-channel Memory
  5 KB (648 words) - 17:43, 6 December 2018
• bitmain/sophon/bm1680
  |max memory=16 GiB The chip consists of five subsystems: [[NPU]], [[MCU]], Chip Link, Memory, and Peripherals.
  4 KB (603 words) - 09:59, 11 August 2018
• intel/cores/coffee lake r
  ...51}} and use {{intel|300-series}} chipset ({{intel|Platform Controller Hub|HUB}}). Despite using the same socket, those chips are not backwards-compatible * Dual-channel Memory
  4 KB (523 words) - 01:38, 7 May 2019

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