• intel/crystal well
  '''[[name::Crystal Well]]''' is the [[instance of::codename]] for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris ...two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
  2 KB (371 words) - 02:53, 15 February 2017
• intel/core i7/i7-4950hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  4 KB (404 words) - 16:22, 13 December 2017
• intel/core i7/i7-4960hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (401 words) - 14:24, 12 February 2019
• intel/core i7/i7-4980hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850hq
  ...e [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}. == Cache ==
  3 KB (400 words) - 16:22, 13 December 2017
• intel/core i7/i7-4860hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4870hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (386 words) - 09:14, 26 December 2017
• intel/core i7/i7-4750hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-4760hq
  ...tel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal Well}}. == Cache ==
  3 KB (397 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770hq
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (398 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770r
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  4 KB (406 words) - 16:22, 13 December 2017
• intel/core i5/i5-4670r
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  4 KB (404 words) - 16:19, 13 December 2017
• intel/core i5/i5-4570r
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (401 words) - 16:19, 13 December 2017
• intel/core i7/i7-4860eq
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (396 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850eq
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (391 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1284l v3
  ...integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache. == Cache ==
  3 KB (399 words) - 16:27, 13 December 2017
• intel/core i7/i7-5775c
  == Cache == {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
  4 KB (460 words) - 15:03, 24 March 2019
• intel/iris graphics/540
  ...ake U|l=core}}) processors. This GPU incorporates 64 MiB of [[eDRAM]] side cache on-chip for added performance. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}
  4 KB (470 words) - 17:01, 9 July 2017
• intel/iris graphics/550
  ...ake U|l=core}}) processors. This GPU incorporates 64 MiB of [[eDRAM]] side cache on-chip for added performance. {{comp table header 1|cols=Launched, Price, Family, Cores, Threads, %L3$, %L4$, TDP, %Frequency, Turbo, Max Mem, GPU, %Frequency, Turbo}}
  4 KB (475 words) - 06:43, 8 May 2018
• intel/core i3/i3-6167u
  ...emory. The 6167U comes with an additional 64 MiB of [[embedded DRAM]] side cache. == Cache ==
  4 KB (631 words) - 16:18, 13 December 2017

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)