...28 and 40 [[PCIe]] lanes are possible with a core ratio of up to x80 the [[BCLK]]. [[File:haswell bclk.png|300px|right]]

...Hz. Note that this has changed from 133 MHz in previous architectures. The BCLK is the reference edge for all the clock domains. Because the core slices an [[File:sandy bridge bclk.png|left|300px]]

** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals) ...ocessor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).

...ocessor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]). * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time

...ocessor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]). * '''BCLK''' - Bus/Base Clock - The system bus interface frequency (once upon a time

...mit depends on the active core count and the [[microarchitecture]]'s {{x86|BCLK}}. The turbo frequency per each number of active cores is some multiple (ca ! µarch !! {{x86|BCLK}} ||   || µarch !! {{x86|BCLK}}

** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 MHz intervals)