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{{x86 title|Extensions}}{{x86 isa main}}
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{{x86 title|Extensions}}
 
The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations that added new [[instructions]] to performs specific tasks. These collections of new instructions are grouped into '''extensions'''. Different microprocessor models have different levels of support for certain extensions.
 
The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations that added new [[instructions]] to performs specific tasks. These collections of new instructions are grouped into '''extensions'''. Different microprocessor models have different levels of support for certain extensions.
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== Overview ==
 
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The [[x86]] ISA has been developed over the course of forty years. Various extensions have been proposed and implemented by various vendors in order to enhance the functionality of the base instruction set.
 
  
 
== Timeline ==
 
== Timeline ==
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| [[1978]] || {{\|Real}} || {{intel|8086|l=arch}} || Original Real mode
 
| [[1978]] || {{\|Real}} || {{intel|8086|l=arch}} || Original Real mode
 
|-
 
|-
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| [[1982]] || {{\|Protected}} || {{intel|80286|l=arch}} || Protected mode
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| [[1982]] || {{\|Protected}} || {{intel|80186|l=arch}} || Protected mode
 
|-
 
|-
 
| [[1985]] || {{\|SMM}} || {{intel|80386|l=arch}} || System Management Mode
 
| [[1985]] || {{\|SMM}} || {{intel|80386|l=arch}} || System Management Mode
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| [[1999]] || {{\|Professional 3DNow!}} || || A name given by AMD for {{\|E3DNow!}} + {{\|SSE}}
 
| [[1999]] || {{\|Professional 3DNow!}} || || A name given by AMD for {{\|E3DNow!}} + {{\|SSE}}
 
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|-
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| [[1999]] || {{\|EMMX}} || {{intel|P6|l=arch}} || Extended MMX; an extension to MMX
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| [[1999]] || {{\|EMMX}} || {{\|P6}} || Extended MMX; an extension to MMX
 
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| [[2001]] || {{x86|SSE2}} || {{intel|P6|l=arch}} || Attempt to replace the original {{\|MMX}} instructions; wider {{x86|XMM}} registers offer better performance
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| [[2001]] || {{x86|SSE2}} || {{intel|P6|l=arch}} || Attempt to replace the original {{\|MMX}} instructions; use wider {{x86|XMM}} registers have offer better performance
 
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| [[2004]] || {{x86|SSE3}} || {{intel|Core|l=arch}} || Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
 
| [[2004]] || {{x86|SSE3}} || {{intel|Core|l=arch}} || Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register
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| [[2008]] || {{x86||SSE4}} || || Streaming SIMD Extensions 4; Another name for SSE4.1 + SSE4.2
 
| [[2008]] || {{x86||SSE4}} || || Streaming SIMD Extensions 4; Another name for SSE4.1 + SSE4.2
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| [[2009]] || {{x86|XOP}} || {{amd|Bulldozer|l=arch}} || eXtended Operations; various vector operations
 
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| [[2010]] || {{x86|CLMUL}} || {{intel|Westmere|l=arch}} || Carry-less multiplication of two registers
 
| [[2010]] || {{x86|CLMUL}} || {{intel|Westmere|l=arch}} || Carry-less multiplication of two registers
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| [[2012]] || {{x86|F16C}} || {{intel|Ivy Bridge|l=arch}} || Extension for performing half-precision <-> single-precision conversions
 
| [[2012]] || {{x86|F16C}} || {{intel|Ivy Bridge|l=arch}} || Extension for performing half-precision <-> single-precision conversions
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| [[2011]] || {{x86|XOP}} || {{amd|Bulldozer|l=arch}} || eXtended Operations; various vector operations
 
 
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| [[2011]] || {{x86|FMA4}} || {{amd|Bulldozer|l=arch}} || 4-operands fused multiply-add
 
| [[2011]] || {{x86|FMA4}} || {{amd|Bulldozer|l=arch}} || 4-operands fused multiply-add
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| [[2011]] || {{x86|LWP}} || {{amd|Bulldozer|l=arch}} || Lightweight Profiling
 
 
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| [[2011]] || {{x86|SMX}} || {{intel|Nehalem|l=arch}} || Safer Mode Extensions; instructions needed to facilitate trust decisions (Part of Intel's {{intel|Trusted Execution Technology}})
 
| [[2011]] || {{x86|SMX}} || {{intel|Nehalem|l=arch}} || Safer Mode Extensions; instructions needed to facilitate trust decisions (Part of Intel's {{intel|Trusted Execution Technology}})
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| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions
 
| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions
 
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| [[2014]] || {{x86|ADX}} || {{intel|Broadwell|l=arch}} || Multi-Precision Add-Carry Instruction extension  
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| [[2014]] || {{x86|ADX}} || {{intel|Haswell|l=arch}} || Multi-Precision Add-Carry Instruction extension  
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| [[2014]] || {{x86|RdRand}} || {{intel|Broadwell|l=arch}} || Part of Secure Key Technology extension (RdRand, RDSEED)
 
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| [[2014]] || {{x86|PREFETCH}} || {{intel|Broadwell|l=arch}} || PREFETCH instructions (previously part of {{\|3DNow!}})
 
 
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| [[2015]] || {{x86|AVX-512}} || {{intel|Airmont|l=arch}} || 512 bit register operations
 
| [[2015]] || {{x86|AVX-512}} || {{intel|Airmont|l=arch}} || 512 bit register operations
 
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| [[2015]] || {{x86|MPX}} || {{intel|Skylake|l=arch}} || Memory Protection Extensions
 
| [[2015]] || {{x86|MPX}} || {{intel|Skylake|l=arch}} || Memory Protection Extensions
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| [[2015]] || {{x86|SGX}} || {{intel|Skylake|l=arch}} || Software Guard Extensions
 
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|-
 
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| [[2016]] || {{x86|SHA}} || {{intel|Goldmont|l=arch}} || SHA Extensions
 
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| [[2017]] || {{x86|SME}} || {{amd|Zen|l=arch}} || Secure Memory Extensions
 
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| [[2019]] || {{x86|TME}} || {{intel|Ice Lake (server)|Ice Lake|l=arch}} || Total Memory Encryption
 
 
|}
 
|}
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== Experimental Extensions ==
 
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{| class="wikitable"
 
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! !! Extension !! First [[µarch]] !! Description
 
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|-
 
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| [[2008]] || {{\|L1OM}} || {{intel|Larrabee|l=arch}} || 512-bit vector extension
 
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|-
 
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| [[2010]] || {{\|K1OM}} || {{intel|Knights Corner|l=arch}} || 512-bit vector extension
 
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|}
 
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== Backwards compatibility ==
 
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Generally speaking, all extensions are supported from their introductory date to present day. Extensions introduced by AMD's {{amd|K6-2|l=arch}} (i.e., {{x86|3DNow!}} & {{x86|E3DNow!}}) and those introduced by AMD's {{amd|Bulldozer|l=arch}} (i.e., {{x86|FMA4}}, {{x86|XOP}}, {{x86|LWP}}, and later {{x86|TBM}}) have been obsoleted. Note that {{amd|Zen|l=arch}}, at least for first stepping, still offered FMA4 support even though it's not indicated by {{x86|CPUID}}.
 
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== See also ==
 
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* {{arm|Versions|ARM's Versions}}
 
  
 
[[Category:x86]]
 
[[Category:x86]]

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