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Difference between revisions of "pezy/pezy-scx/pezy-sc2"
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{{pezy title|PEZY-SC2}} | {{pezy title|PEZY-SC2}} | ||
{{mpu | {{mpu | ||
− | | future | + | |future=Yes |
− | | name | + | |name=PEZY-SC2 |
− | | no image | + | |no image=Yes |
− | + | |designer=PEZY | |
− | + | |manufacturer=TSMC | |
− | + | |model number=PEZY-SC2 | |
− | | designer | + | |market=Supercomputer |
− | | manufacturer | + | |first announced=2015 |
− | | model number | + | |first launched=2016 |
− | + | |frequency=1,000 MHz | |
− | | market | + | |process=16 nm |
− | | first announced | + | |technology=CMOS |
− | | first launched | + | |die area=620 mm² |
− | | | + | |core count=2,048 |
− | | | + | |power=200 W |
+ | |v core=0.8 V | ||
+ | }} | ||
+ | '''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor. | ||
− | + | PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's [[16 nm process]]. | |
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− | + | {{unknown features}} | |
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− | | | + | == Memory controller == |
− | | | + | {{memory controller |
− | | | + | |type=DDR4-2666 |
− | | | + | |ecc=Yes |
− | | | + | |controllers=8 |
− | | | + | |channels=8 |
− | | | + | |max bandwidth=158.95 GiB/s |
− | | | + | |bandwidth schan=19.89 GiB/s |
− | | | + | |bandwidth dchan=39.72 GiB/s |
− | | | + | |bandwidth qchan=79.47 GiB/s |
+ | |bandwidth ochan=158.95 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
}} | }} | ||
− | |||
− | + | {{memory controller | |
+ | |wide-io clock=2,000 MHz | ||
+ | |wide-io width=1,024 bit | ||
+ | |channels=4 | ||
+ | |max bandwidth=1.863 TiB/s | ||
+ | }} | ||
− | + | == Expansions == | |
− | {{ | + | {{expansions |
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 32 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | | uart = Yes | ||
+ | | gp io = Yes | ||
+ | }} |
Revision as of 06:29, 23 June 2017
Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.
PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.
Memory controller
Integrated Memory Controller
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Integrated Memory Controller
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Expansions
Expansion Options
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Facts about "PEZY-SC2 - PEZY"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC2 - PEZY#io + |
has ecc memory support | true + and false + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + and 1,907.712 GiB/s (1,953,497.088 MiB/s, 2,048.39 GB/s, 2,048,390.163 MB/s, 1.863 TiB/s, 2.048 TB/s) + |
max memory channels | 8 + and 4 + |
max pcie lanes | 32 + |
supported memory type | DDR4-2666 + |