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Difference between revisions of "pezy/pezy-scx/pezy-sc2"
< pezy‎ | pezy-scx

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{{pezy title|PEZY-SC2}}
 
{{pezy title|PEZY-SC2}}
 
{{mpu
 
{{mpu
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| future             = Yes
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|future=Yes
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| name               = PEZY-SC2
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|name=PEZY-SC2
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| no image           = Yes
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|no image=Yes
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| image              =
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|designer=PEZY
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| image size          =
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|manufacturer=TSMC
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| caption            =
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|model number=PEZY-SC2
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| designer           = PEZY
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|market=Supercomputer
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| manufacturer       = TSMC
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|first announced=2015
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| model number       = PEZY-SC2
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|first launched=2016
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| part number        =
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|frequency=1,000 MHz
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| market             = Industrial
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|process=16 nm
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| first announced     = 2015
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|technology=CMOS
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| first launched     = 2016
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|die area=620 mm²
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| last order          =  
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|core count=2,048
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| last shipment      =  
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|power=200 W
 +
|v core=0.8 V
 +
}}
 +
'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.
  
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| family              =
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PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's [[16 nm process]].
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| series              =
 
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| locked              =
 
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| frequency          = 999.99 MHz
 
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| bus type            =
 
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| bus speed          = 66.66 MHz
 
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| bus rate            =
 
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| clock multiplier    = 15
 
  
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| microarch          =
 
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| platform            =
 
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| chipset            =
 
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| core name          =
 
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| core family        =
 
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| core model          =
 
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| core stepping      =
 
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| process            = 16 nm
 
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| transistors        =
 
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| technology          = CMOS
 
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| die area            = 400-500 mm²
 
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| die width          =
 
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| die length          =
 
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| word size          =
 
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| core count          = 4,096
 
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| thread count        =
 
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| max cpus            =
 
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| max memory          =
 
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| max memory addr    =
 
  
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| electrical          = Yes
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{{unknown features}}
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| power              = 100 W
 
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| v core              =
 
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| v core tolerance    =
 
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| v io                =
 
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| v io tolerance      =
 
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| sdp                =
 
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| tdp                =
 
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| ctdp down          =
 
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| ctdp down frequency =
 
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| ctdp up            =
 
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| ctdp up frequency  =
 
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| temp min            =
 
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| temp max            =
 
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| tjunc min          = <!-- °C -->
 
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| tjunc max          =
 
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| tcase min          =
 
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| tcase max          =
 
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| tstorage min        =
 
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| tstorage max        =
 
  
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| packaging          =  
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== Memory controller ==
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| package 0          =  
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{{memory controller
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| package 0 type      =  
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|type=DDR4-2666
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| package 0 pins      =  
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|ecc=Yes
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| package 0 pitch    =  
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|controllers=8
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| package 0 width    =  
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|channels=8
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| package 0 length    =  
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|max bandwidth=158.95 GiB/s
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| package 0 height    =  
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|bandwidth schan=19.89 GiB/s
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| socket 0            =  
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|bandwidth dchan=39.72 GiB/s
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| socket 0 type      =  
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|bandwidth qchan=79.47 GiB/s
 +
|bandwidth ochan=158.95 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 
}}
 
}}
−
'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] set to be released in late 2016 or early 2017. The SC2 is planned to have 4096 cores, 4 times as many cores as its predecessor. Unlike the {{pezy|PEZY-SC}} which had 2 {{armh|ARM926}}, the SC2 will be replaced by 12 {{mips|MIPS64}} cores.
 
  
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PEZY-SC2 is planned to operate at 1 GHz and consume around 100 W while delivering performance in the order of 16.4 TFLOPS (single-precision) and 8.2 TFLOPS (double precision). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's [[16 nm process]].
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{{memory controller
 +
|wide-io clock=2,000 MHz
 +
|wide-io width=1,024 bit
 +
|channels=4
 +
|max bandwidth=1.863 TiB/s
 +
}}
  
−
 
+
== Expansions ==
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{{unknown features}}
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{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 32
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
| uart              = Yes
 +
| gp io              = Yes
 +
}}

Revision as of 06:29, 23 June 2017

Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.

PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate2,000 MHz
Width1,024 bit
Channels4
Max Bandwidth1.863 TiB/s
1,907.712 GiB/s
1,953,497.088 MiB/s
2,048.39 GB/s
2,048,390.163 MB/s
2.048 TB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes32
Configsx16, x8, x4
UART
GP I/OYes
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Facts about "PEZY-SC2 - PEZY"
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PEZY-SC2 - PEZY#io +
has ecc memory supporttrue + and false +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + and 1,907.712 GiB/s (1,953,497.088 MiB/s, 2,048.39 GB/s, 2,048,390.163 MB/s, 1.863 TiB/s, 2.048 TB/s) +
max memory channels8 + and 4 +
max pcie lanes32 +
supported memory typeDDR4-2666 +