Editing mips/mips32 instruction set

{{ISA|
|name          =  MIPS32
|designer      =  [[MIPS Technologies, Inc.]]
|bits          =  32-bits
|introduced    =  1999
|design        =  RISC
|type          =  Register-Register
|encoding      =  Fixed-length
|branching     =  Condition Register
|endianness    =  Bi-endian
|extensions    =  [[SPECIAL2]], [[COP2]], [[LWC2]], [[SWC2]], [[LDC2]], [[SDC2]]
|application   =  [[MIPS16e]], [[MIPS MCU]], [[MIPS SmartMIPS]]
|multimedia    =  [[MIPS-3D]]
|gpr           =  32
|fpr           =  32
}}

The '''MIPS32 instruction set''' is an instruction set standard published in 1999 that was promulgated by [[MIPS Technologies]] after its [[Wikipedia:demerger|demerger]] from [[Silicon Graphics]] in 1998. The MIPS32 instruction set was developed along side the [[MIPS64 Instruction Set]] which includes 64-bit instructions. The MIP32 standard included coprocessor 0 control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most [[MIPS|MIPS CPUs]]. Dur to it's relative simply, the MIP32 instruction set is also the most common instruction set thought in computer architecture university courses.



== Instructions list ==
Below is a list of the MIPS32 Instruction Set

* CPU Instructions
** [[#Arithmetic instructions|Arithmetic Instructions]]
** [[#Branch instructions|Branch Instructions]]
** [[#Jump instructions|Jump Instructions]]
** [[#Control instructions|Control Instructions]]
** [[#Memory control instructions|Memory Control Instructions]]
** [[#Logical instruction|Logical Instruction]]
** [[#Insert/Extract instructions|Insert/Extract Instructions]]
** [[#Move instructions|Move Instructions]]
** [[#Shift instructions|Shift Instructions]]
** [[#Trap instructions|Trap Instructions]]
* FPU Instructions
** [[#Arithmetic instructions|Arithmetic Instructions]]
** [[#Branch instructions|Branch Instructions]]
** [[#Compare instructions|Compare Instructions]]
** [[#Convert instructions|Convert Instructions]]
** [[#Memory control instructions|Memory Control Instructions]]
** [[#Move instructions|Move Instructions]]
* Coprocessor Instructions
** [[#Branch instructions|Branch Instructions]]
** [[#Execute instructions|Execute Instructions]]
** [[#Memory control instructions|Memory control Instructions]]
** [[#Move instructions|Move Instructions]]
* [[#Privileged instructions|Privileged Instructions]]
* [[#EJTAG instructions|EJTAG Instructions]]

=== Arithmetic instructions ===

{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[ADD - MIPS|ADD]] || Add Word
|-
| [[ADDI - MIPS|ADDI]] || Add Immediate Word
|-
| [[ADDIU - MIPS|ADDIU]] || Add Immediate Unsigned Word
|-
| [[ADDU - MIPS|ADDU]] || Add Unsigned Word
|-
| [[CLO - MIPS|CLO]] || Count Leading Ones in Word
|-
| [[CLZ - MIPS|CLZ]] || Count Leading Zeros in Word
|-
| [[DIV - MIPS|DIV]] || Divide Word
|-
| [[DIVU - MIPS|DIVU]] || Divide Unsigned Word
|-
| [[MADD - MIPS|MADD]] || Multiply and Add Word to Hi, Lo
|-
| [[MADDU - MIPS|MADDU]] || Multiply and Add Unsigned Word to Hi, Lo
|-
| [[MSUB - MIPS|MSUB]] || Multiply and Subtract Word to Hi, Lo
|-
| [[MSUBU - MIPS|MSUBU]] || Multiply and Subtract Unsigned Word to Hi, Lo
|-
| [[MUL - MIPS|MUL]] || Multiply Word to GPR
|-
| [[MULT - MIPS|MULT]] || Multiply Word
|-
| [[MULTU - MIPS|MULTU]] || Multiply Unsigned Word
|-
| [[SEB - MIPS|SEB]] || Sign-Extend Byte
|-
| [[SEH - MIPS|SEH]] || Sign-Extend Halftword
|-
| [[SLT - MIPS|SLT]] || Set on Less Than
|-
| [[SLTI - MIPS|SLTI]] || Set on Less Than Immediate
|-
| [[SLTIU - MIPS|SLTIU]] || Set on Less Than Immediate Unsigned
|-
| [[SLTU - MIPS|SLTU]] || Set on Less Than Unsigned
|-
| [[SUB - MIPS|SUB]] || Subtract Word
|-
| [[SUBU - MIPS|SUBU]] || Subtract Unsigned Word
|}

=== Branch instructions ===
Note that all the likely branches have been obsoleted; they will be removed in future revisions of the MIPS32 architecture. Software is strongly discouraged from using these instructions.

{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[B - MIPS|B]] || Unconditional Branch
|-
| [[BAL - MIPS|BAL]] || Branch and Link
|-
| [[BEQ - MIPS|BEQ]] || Branch on Equal
|-
| [[BGEZ - MIPS|BGEZ]] || Branch on Greater Than or Equal to Zero
|-
| [[BGEZAL - MIPS|BGEZAL]] || Branch on Greater Than or Equal to Zero and Link
|-
| [[BGTZ - MIPS|BGTZ]] || Branch on Greater Than Zero
|-
| [[BLEZ - MIPS|BLEZ]] || Branch on Less Than or Equal to Zero
|-
| [[BLTZ - MIPS|BLTZ]] || Branch on Less Than Zero
|-
| [[BLTZAL - MIPS|BLTZAL]] || Branch on Less Than Zero and Link
|-
| [[BNE - MIPS|BNE]] || Branch on Not Equal
|-
| <strike>[[BEQL - MIPS|BEQL]]</strike> || Branch on Equal Likely
|-
| <strike>[[BGEZALL - MIPS|BGEZALL]]</strike> || Branch on Greater Than or Equal to Zero and Link Likely
|-
| <strike>[[BGEZL - MIPS|BGEZL]]</strike> || Branch on Greater Than or Equal to Zero Likely
|-
| <strike>[[BGTZL - MIPS|BGTZL]]</strike> || Branch on Greater Than Zero Likely
|-
| <strike>[[BLEZL - MIPS|BLEZL]]</strike> || Branch on Less Than or Equal to Zero Likely
|-
| <strike>[[BLTZALL - MIPS|BLTZALL]]</strike> || Branch on Less Than Zero and Link Likely
|-
| <strike>[[BLTZL - MIPS|BLTZL]]</strike> || Branch on Less Than Zero Likely
|-
| <strike>[[BNEL - MIPS|BNEL]]</strike> || Branch on Not Equal Likely
|}

=== Jump instructions ===

{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[J - MIPS|J]] || Jump
|-
| [[JAL - MIPS|JAL]] || Jump and Link
|-
| [[JALR - MIPS|JALR]] || Jump and Link Register
|-
| [[JALR.HB  - MIPS|JALR.HB ]]|| Jump and Link Register with Hazard Barrier
|-
| [[JALX - MIPS|JALX]] || Jump and Link Exchange
|-
| [[JR - MIPS|JR]] || Jump Register
|-
| [[JR.HB - MIPS|JR.HB]] || Jump Register with Hazard Barrier
|}

=== Control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[EHB - MIPS|EHB]] || Execution Hazard Barrier
|-
| [[NOP - MIPS|NOP]] || No Operation
|-
| [[PAUSE - MIPS|PAUSE]] || Wait for LLBit to Clear
|-
| [[SSNOP - MIPS|SSNOP]] || Superscalar No Operation
|}

=== Memory control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[LB - MIPS|LB]] ||  Load Byte
|-
| [[LBE - MIPS|LBE]] || Load Byte EVA
|-
| [[LBU - MIPS|LBU]] || Load Byte Unsigned
|-
| [[LBUE - MIPS|LBUE]] || Load Byte Unsigned EVA
|-
| [[LH - MIPS|LH]] || Load Halfword
|-
| [[LHE - MIPS|LHE]] || Load Halfword EVA
|-
| [[LHU - MIPS|LHU]] || Load Halfword Unsigned
|-
| [[LHUE - MIPS|LHUE]] || Load Halfword Unsigned EVA
|-
| [[LL - MIPS|LL]] || Load Linked Word
|-
| [[LLE - MIPS|LLE]] || Load Linked Word-EVA
|-
| [[LW - MIPS|LW]] || Load Word
|-
| [[LWE - MIPS|LWE]] || Load Word EVA
|-
| [[LWL - MIPS|LWL]] || Load Word Left
|-
| [[LWLE - MIPS|LWLE]] || Load Word Left EVA
|-
| [[LWR - MIPS|LWR]] || Load Word Right
|-
| [[LWRE - MIPS|LWRE]] || Load Word Right EVA
|-
| [[PREF - MIPS|PREF]] || Prefetch
|-
| [[PREFE - MIPS|PREFE]] || Prefetch-EVA
|-
| [[SB - MIPS|SB]] || Store Byte
|-
| [[SBE - MIPS|SBE]] || Store Byte EVA
|-
| [[SC - MIPS|SC]] || Store Conditional Word
|-
| [[SCE - MIPS|SCE]] || Store Conditional Word EVA
|-
| [[SH - MIPS|SH]] || Store Halfword
|-
| [[SHE - MIPS|SHE]] || Store Halfword EVA
|-
| [[SW - MIPS|SW]] || Store Word
|-
| [[SWE - MIPS|SWE]] || Store Word EVA
|-
| [[SWL - MIPS|SWL]] || Store Word Left
|-
| [[SWLE - MIPS|SWLE]] || Store Word Left EVA
|-
| [[SWR - MIPS|SWR]] || Store Word Right
|-
| [[SWRE - MIPS|SWRE]] || Store Word Right EVA
|-
| [[SYNC - MIPS|SYNC]] || Synchronize Shared Memory
|-
| [[SYNCI - MIPS|SYNCI]] || Synchronize Caches to Make Instruction Writes Effective
|}

=== Logical instruction ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[AND - MIPS|AND]] || And
|-
| [[ANDI - MIPS|ANDI]] || And Immediate
|-
| [[LUI - MIPS|LUI]] || Load Upper Immediate
|-
| [[NOR - MIPS|NOR]] || Not Or
|-
| [[OR - MIPS|OR]] || Or
|-
| [[ORI - MIPS|ORI]] || Or Immediate
|-
| [[XOR - MIPS|XOR]] || Exclusive Or
|-
| [[XORI - MIPS|XORI]] || Exclusive Or Immediate
|}

=== Insert/Extract instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[EXT - MIPS|EXT]] || Extract Bit Field
|-
| [[INS - MIPS|INS]] || Insert Bit Field
|-
| [[WSBH - MIPS|WSBH]] || Word Swap Bytes Within Halfwords
|}

=== Move instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[MFHI - MIPS|MFHI]] || Move From HI Register
|-
| [[MFLO - MIPS|MFLO]] || Move From LO Register
|-
| [[MOVF - MIPS|MOVF]] || Move Conditional on Floating Point False
|-
| [[MOVN - MIPS|MOVN]] || Move Conditional on Not Zero
|-
| [[MOVT - MIPS|MOVT]] || Move Conditional on Floating Point True
|-
| [[MOVZ - MIPS|MOVZ]] || Move Conditional on Zero
|-
| [[MTHI - MIPS|MTHI]] || Move To HI Register
|-
| [[MTLO - MIPS|MTLO]] || Move To LO Register
|-
| [[RDHWR - MIPS|RDHWR]] || Read Hardware Register
|}

=== Shift instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[ROTR - MIPS|ROTR]] || Rotate Word Right
|-
| [[ROTRV - MIPS|ROTRV]] || Rotate Word Right Variable
|-
| [[SLL - MIPS|SLL]] || Shift Word Left Logical
|-
| [[SLLV - MIPS|SLLV]] || Shift Word Left Logical Variable
|-
| [[SRA - MIPS|SRA]] || Shift Word Right Arithmetic
|-
| [[SRAV - MIPS|SRAV]] || Shift Word Right Arithmetic Variable
|-
| [[SRL - MIPS|SRL]] || Shift Word Right Logical
|-
| [[SRLV - MIPS|SRLV]] || Shift Word Right Logical Variable
|}

=== Trap instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[BREAK - MIPS|BREAK]] || Breakpoint
|-
| [[SYSCALL - MIPS|SYSCALL]] || System Call
|-
| [[TEQ - MIPS|TEQ]] || Trap if Equal
|-
| [[TEQI - MIPS|TEQI]] || Trap if Equal Immediate
|-
| [[TGE - MIPS|TGE]] || Trap if Greater or Equal
|-
| [[TGEI - MIPS|TGEI]] || Trap if Greater of Equal Immediate
|-
| [[TGEIU - MIPS|TGEIU]] || Trap if Greater or Equal Immediate Unsigned
|-
| [[TGEU - MIPS|TGEU]] || Trap if Greater or Equal Unsigned
|-
| [[TLT - MIPS|TLT]] || Trap if Less Than
|-
| [[TLTI - MIPS|TLTI]] || Trap if Less Than Immediate
|-
| [[TLTIU - MIPS|TLTIU]] || Trap if Less Than Immediate Unsigned
|-
| [[TLTU - MIPS|TLTU]] || Trap if Less Than Unsigned
|-
| [[TNE - MIPS|TNE]] || Trap if Not Equal
|-
| [[TNEI - MIPS|TNEI]] || Trap if Not Equal Immediate
|}


== FPU instructions ==

=== Arithmetic instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[ABS.fmt - MIPS|ABS.fmt]] || Floating Point Absolute Value
|-
| [[ADD.fmt - MIPS|ADD.fmt]] || Floating Point Add
|-
| [[DIV.fmt - MIPS|DIV.fmt]] || Floating Point Divide
|-
| [[MADD.fmt - MIPS|MADD.fmt]] || Floating Point Multiply Add
|-
| [[MSUB.fmt - MIPS|MSUB.fmt]] || Floating Point Multiply Subtract
|-
| [[MUL.fmt - MIPS|MUL.fmt]] || Floating Point Multiply
|-
| [[NEG.fmt - MIPS|NEG.fmt]] || Floating Point Negate
|-
| [[NMADD.fmt - MIPS|NMADD.fmt]] || Floating Point Negative Multiply Add
|-
| [[NMSUB.fmt - MIPS|NMSUB.fmt]] || Floating Point Negative Multiply Subtract
|-
| [[RECIP.fmt - MIPS|RECIP.fmt]] || Reciprocal Approximation
|-
| [[RSQRT.fmt - MIPS|RSQRT.fmt]] || Reciprocal Square Root Approximation
|-
| [[SQRT.fmt - MIPS|SQRT.fmt]] || Floating Point Square Root
|-
| [[SUB.fmt - MIPS|SUB.fmt]] || Floating Point Subtract
|}


=== Branch instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[BC1F - MIPS|BC1F]] || Branch on FP False
|-
| [[BC1T - MIPS|BC1T]] || Branch on FP True
|-
| <strike>[[BC1FL - MIPS|BC1FL]]</strike> || Branch on FP False Likely
|-
| <strike>[[BC1TL - MIPS|BC1TL]]</strike> || Branch on FP True Likely
|}

=== Compare instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[C.cond.fmt - MIPS|C.cond.fmt]] || Floating Point Compare
|}

=== Convert instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[ALNV.PS - MIPS|ALNV.PS]] || Floating Point Align Variable
|-
| [[CEIL.L.fmt - MIPS|CEIL.L.fmt]] || Floating Point Ceiling Convert to Long Fixed Point
|-
| [[CEIL.W.fmt - MIPS|CEIL.W.fmt]] || Floating Point Ceiling Convert to Word Fixed Point
|-
| [[CVT.D.fmt - MIPS|CVT.D.fmt]] || Floating Point Convert to Double Floating Point
|-
| [[CVT.L.fmt - MIPS|CVT.L.fmt]] || Floating Point Convert to Long Fixed Point
|-
| [[CVT.PS.S - MIPS|CVT.PS.S]] || Floating Point Convert Pair to Paired Single
|-
| [[CVT.S.PL - MIPS|CVT.S.PL]] || Floating Point Convert Pair Lower to Single Floating Point
|-
| [[CVT.S.PU - MIPS|CVT.S.PU]] || Floating Point Convert Pair Upper to Single Floating Point
|-
| [[CVT.S.fmt - MIPS|CVT.S.fmt]] || Floating Point Convert to Single Floating Point
|-
| [[CVT.W.fmt - MIPS|CVT.W.fmt]] || Floating Point Convert to Word Fixed Point
|-
| [[FLOOR.L.fmt - MIPS|FLOOR.L.fmt]] || Floating Point Floor Convert to Long Fixed Point
|-
| [[FLOOR.W.fmt - MIPS|FLOOR.W.fmt]] || Floating Point Floor Convert to Word Fixed Point
|-
| [[PLL.PS - MIPS|PLL.PS]] || Pair Lower Lower
|-
| [[PLU.PS - MIPS|PLU.PS]] || Pair Lower Upper
|-
| [[PUL.PS - MIPS|PUL.PS]] || Pair Upper Lower
|-
| [[PUU.PS - MIPS|PUU.PS]] || Pair Upper Upper
|-
| [[ROUND.L.fmt - MIPS|ROUND.L.fmt]] || Floating Point Round to Long Fixed Point
|-
| [[ROUND.W.fmt - MIPS|ROUND.W.fmt]] || Floating Point Round to Word Fixed Point
|-
| [[TRUNC.L.fmt - MIPS|TRUNC.L.fmt]] || Floating Point Truncate to Long Fixed Point
|-
| [[TRUNC.W.fmt - MIPS|TRUNC.W.fmt]] || Floating Point Truncate to Word Fixed Point
|}


=== Memory control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[LDC1 - MIPS|LDC1]] || Load Doubleword to Floating Point
|-
| [[LDXC1 - MIPS|LDXC1]] || Load Doubleword Indexed to Floating Point
|-
| [[LUXC1 - MIPS|LUXC1]] || Load Doubleword Indexed Unaligned to Floating Point
|-
| [[LWC1 - MIPS|LWC1]] || Load Word to Floating Point
|-
| [[LWXC1 - MIPS|LWXC1]] || Load Word Indexed to Floating Point
|-
| [[PREFX - MIPS|PREFX]] || Prefetch Indexed
|-
| [[SDC1 - MIPS|SDC1]] || Store Doubleword from Floating Point
|-
| [[SDXC1 - MIPS|SDXC1]] || Store Doubleword Indexed from Floating Point
|-
| [[SUXC1 - MIPS|SUXC1]] || Store Doubleword Indexed Unaligned from Floating Point
|-
| [[SWC1 - MIPS|SWC1]] || Store Word from Floating Point
|-
| [[SWXC1 - MIPS|SWXC1]] || Store Word Indexed from Floating Point
|}


=== Move instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[CFC1 - MIPS|CFC1]] || Move Control Word from Floating Point
|-
| [[CTC1 - MIPS|CTC1]] || Move Control Word to Floating Point
|-
| [[MFC1 - MIPS|MFC1]] || Move Word from Floating Point
|-
| [[MFHC1 - MIPS|MFHC1]] || Move Word from High Half of Floating Point Register
|-
| [[MOV.fmt - MIPS|MOV.fmt]] || Floating Point Move
|-
| [[MOVF.fmt - MIPS|MOVF.fmt]] || Floating Point Move Conditional on Floating Point False
|-
| [[MOVN.fmt - MIPS|MOVN.fmt]] || Floating Point Move Conditional on Not Zero
|-
| [[MOVT.fmt - MIPS|MOVT.fmt]] || Floating Point Move Conditional on Floating Point True
|-
| [[MOVZ.fmt - MIPS|MOVZ.fmt]] || Floating Point Move Conditional on Zero
|-
| [[MTC1 - MIPS|MTC1]] || Move Word to Floating Point
|-
| [[MTHC1 - MIPS|MTHC1]] || Move Word to High Half of Floating Point Register
|}

== Coprocessor instructions ==

=== Branch instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[BC2F - MIPS|BC2F]] || Branch on COP2 False
|-
| [[BC2T - MIPS|BC2T]] || Branch on COP2 True
|-
| <strike>[[BC2FL - MIPS|BC2FL]]</strike> || Branch on COP2 False Likely
|-
| <strike>[[BC2TL - MIPS|BC2TL]]</strike> || Branch on COP2 True Likely
|}


=== Execute instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[COP2 - MIPS|COP2]] || Coprocessor Operation to Coprocessor 2
|}

=== Memory control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[DC2 - MIPS|DC2]] || Load Doubleword to Coprocessor 2
|-
| [[LWC2 - MIPS|LWC2]] || Load Word to Coprocessor 2
|-
| [[SDC2 - MIPS|SDC2]] || Store Doubleword from Coprocessor 2
|-
| [[SWC2 - MIPS|SWC2]] || Store Word from Coprocessor 2
|}


=== Move instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[CFC2 - MIPS|CFC2]] || Move Control Word from Coprocessor 2
|-
| [[CTC2 - MIPS|CTC2]] || Move Control Word to Coprocessor 2
|-
| [[MFC2 - MIPS|MFC2]] || Move Word from Coprocessor 2
|-
| [[MFHC2 - MIPS|MFHC2]] || Move Word from High Half of Coprocessor 2 Register
|-
| [[MTC2 - MIPS|MTC2]] || Move Word to Coprocessor 2
|-
| [[MTHC2 - MIPS|MTHC2]] || Move Word to High Half of Coprocessor 2 Register
|}


== Privileged instructions ==
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[CACHE - MIPS|CACHE]] || Perform Cache Operation
|-
| [[CACHEE - MIPS|CACHEE]] || Perform Cache Operation EVA
|-
| [[DI - MIPS|DI]] || Disable Interrupts
|-
| [[EI - MIPS|EI]] || Enable Interrupts
|-
| [[ERET - MIPS|ERET]] || Exception Return
|-
| [[MFC0 - MIPS|MFC0]] || Move from Coprocessor 0
|-
| [[MTC0 - MIPS|MTC0]] || Move to Coprocessor 0
|-
| [[RDPGPR - MIPS|RDPGPR]] || Read GPR from Previous Shadow Set
|-
| [[TLBP - MIPS|TLBP]] || Probe TLB for Matching Entry
|-
| [[TLBR - MIPS|TLBR]] || Read Indexed TLB Entry
|-
| [[TLBWI - MIPS|TLBWI]] || Write Indexed TLB Entry
|-
| [[TLBWR - MIPS|TLBWR]] || Write Random TLB Entry
|-
| [[WAIT - MIPS|WAIT]] || Enter Standby Mode
|-
| [[WRPGPR - MIPS|WRPGPR]] || Write GPR to Previous Shadow Set
|}

== EJTAG instructions ==
{| class="wikitable sortable"
! Mnemonic || Description
|-
| [[DERET - MIPS|DERET]] ||Debug Exception Return
|-
| [[SDBBP - MIPS|SDBBP]] || Software Debug Breakpoint
|}


[[Category:Assembly language]]
[[Category:MIPS]]
[[Category:MIPS32]]
[[Category:RISC instruction set]]
[[Category:Instruction set architecture]]
@@ Line 1: / Line 1: @@
-{{mips title|MIPS32 Instruction Set}}
 {{ISA|
 |name          =  MIPS32
@@ Line 5: / Line 4: @@
 |bits          =  32-bits
 |introduced    =  1999
-|version       =  Revision 5.3
 |design        =  RISC
 |type          =  Register-Register
@@ Line 11: / Line 9: @@
 |branching     =  Condition Register
 |endianness    =  Bi-endian
-|extensions    =  {{mips|SPECIAL2}}, {{mips|COP2}}, {{mips|LWC2}}, {{mips|SWC2}}, {{mips|LDC2}}, {{mips|SDC2}}
+|extensions    =  [[SPECIAL2]], [[COP2]], [[LWC2]], [[SWC2]], [[LDC2]], [[SDC2]]
-|application   =  {{mips|MIPS16e}}, {{mips|MCU}}, {{mips|SmartMIPS}}
+|application   =  [[MIPS16e]], [[MIPS MCU]], [[MIPS SmartMIPS]]
-|multimedia    =  {{mips|MIPS-3D}}
+|multimedia    =  [[MIPS-3D]]
 |gpr           =  32
 |fpr           =  32
-|spr           = {{mips|PRId register|PRId}}
 }}
-The '''MIPS32 instruction set''' is an instruction set standard published in 1999 that was promulgated by [[MIPS Technologies]] after its [[Wikipedia:demerger|demerger]] from [[Silicon Graphics]] in 1998. The MIPS32 instruction set was developed along side the {{mips|MIPS64 Instruction Set}} which includes 64-bit instructions. The MIP32 standard included {{mips|coprocessor 0}} control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most {{mips|CPUs}}. Due to its relative simplicity, the MIP32 instruction set is also the most common instruction set taught in computer architecture university courses.
+The '''MIPS32 instruction set''' is an instruction set standard published in 1999 that was promulgated by [[MIPS Technologies]] after its [[Wikipedia:demerger|demerger]] from [[Silicon Graphics]] in 1998. The MIPS32 instruction set was developed along side the [[MIPS64 Instruction Set]] which includes 64-bit instructions. The MIP32 standard included coprocessor 0 control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most [[MIPS|MIPS CPUs]]. Dur to it's relative simply, the MIP32 instruction set is also the most common instruction set thought in computer architecture university courses.
-The latest MIPS32 revision is revision 5, which added a set of new memory-efficient operations for large memory footprint applications.
-== History ==
-The MIPS32 instruction set architecture was first published in 1999 by [[MIPS Technologies]] by it has demerged from [[Silicon Graphics]] in 1998. MIPS32 is largely a superset of the {{mips|MIPS II}} ISA.
-=== Release 2 ===
-Release 2 was first introduced in revision 1 of the MIPS32 ISA in 2002. Release 2 added 20 new instructions: {{mips|DI}}, {{mips|EHB}}, {{mips|EI}}, {{mips|EXT}}, {{mips|INS}}, {{mips|JALR.HB}}, {{mips|JR.HB}}, {{mips|MFHC1}}, {{mips|MFHC2}}, {{mips|MTHC1}}, {{mips|MTHC2}}, {{mips|RDHWR}}, {{mips|RDPGPR}}, {{mips|ROTR}}, {{mips|ROTRV}}, {{mips|SEB}}, {{mips|SEH}}, {{mips|SYNCI}}, {{mips|WRPGPR}}, and {{mips|WSBH}}. Release 2 also added support for 64-bit FPUs.
-=== Release 3 ===
-Release 3 was first introduced in revision 3 of the MIPS32 ISA in 2010. The release added the {{mips|JALX}} instruction.
-=== Release 4 ===
-Release 4 was skipped because MIPS Technologies was being auctioned off. Officially the reason was given as "Release 4 because the number four is considered by many to be inauspicious or unlucky".<ref>[http://withimagination.imgtec.com/index.php/mips-processors/continuing-evolution-of-the-mips-instruction-set-architecture#sthash.4uCPPXKz.dpuf The continuing evolution of the MIPS Instruction Set Architecture]</ref>
-=== Release 5 ===
-Release 5 was announced in late 2012. The release added a new set of instructions called '''Enhanced Virtual Addressing''' (EVA) to allow more efficient use of memory of larger footprint kernels. The following EVA Load/Store instructions were added: {{mips|LBE}}, {{mips|LBUE}}, {{mips|LHE}}, {{mips|LHUE}}, {{mips|LWE}}, {{mips|SBE}}, {{mips|SHE}}, {{mips|SWE}}, {{mips|CACHEE}}, {{mips|PREFE}}, {{mips|LLE}}, {{mips|SCE}}, {{mips|LWLE}}, {{mips|LWRE}}, {{mips|SWLE}}, {{mips|SWRE}}.
 == Instructions list ==
@@ Line 59: / Line 41: @@
 ** [[#Memory control instructions|Memory Control Instructions]]
 ** [[#Move instructions|Move Instructions]]
-* [[Coprocessor]] Instructions
+* Coprocessor Instructions
 ** [[#Branch instructions|Branch Instructions]]
 ** [[#Execute instructions|Execute Instructions]]
@@ Line 72: / Line 54: @@
 ! Mnemonic || Description
 |-
-| {{mips|ADD}} || Add Word
+| [[ADD - MIPS|ADD]] || Add Word
 |-
-| {{mips|ADDI}} || Add Immediate Word
+| [[ADDI - MIPS|ADDI]] || Add Immediate Word
 |-
-| {{mips|ADDIU}} || Add Immediate Unsigned Word
+| [[ADDIU - MIPS|ADDIU]] || Add Immediate Unsigned Word
 |-
-| {{mips|ADDU}} || Add Unsigned Word
+| [[ADDU - MIPS|ADDU]] || Add Unsigned Word
 |-
-| {{mips|CLO}} || Count Leading Ones in Word
+| [[CLO - MIPS|CLO]] || Count Leading Ones in Word
 |-
-| {{mips|CLZ}} || Count Leading Zeros in Word
+| [[CLZ - MIPS|CLZ]] || Count Leading Zeros in Word
 |-
-| {{mips|DIV}} || Divide Word
+| [[DIV - MIPS|DIV]] || Divide Word
 |-
-| {{mips|DIVU}} || Divide Unsigned Word
+| [[DIVU - MIPS|DIVU]] || Divide Unsigned Word
 |-
-| {{mips|MADD}} || Multiply and Add Word to Hi, Lo
+| [[MADD - MIPS|MADD]] || Multiply and Add Word to Hi, Lo
 |-
-| {{mips|MADDU}} || Multiply and Add Unsigned Word to Hi, Lo
+| [[MADDU - MIPS|MADDU]] || Multiply and Add Unsigned Word to Hi, Lo
 |-
-| {{mips|MSUB}} || Multiply and Subtract Word to Hi, Lo
+| [[MSUB - MIPS|MSUB]] || Multiply and Subtract Word to Hi, Lo
 |-
-| {{mips|MSUBU}} || Multiply and Subtract Unsigned Word to Hi, Lo
+| [[MSUBU - MIPS|MSUBU]] || Multiply and Subtract Unsigned Word to Hi, Lo
 |-
-| {{mips|MUL}} || Multiply Word to GPR
+| [[MUL - MIPS|MUL]] || Multiply Word to GPR
 |-
-| {{mips|MULT}} || Multiply Word
+| [[MULT - MIPS|MULT]] || Multiply Word
 |-
-| {{mips|MULTU}} || Multiply Unsigned Word
+| [[MULTU - MIPS|MULTU]] || Multiply Unsigned Word
 |-
-| {{mips|SEB}} || Sign-Extend Byte
+| [[SEB - MIPS|SEB]] || Sign-Extend Byte
 |-
-| {{mips|SEH}} || Sign-Extend Halfword
+| [[SEH - MIPS|SEH]] || Sign-Extend Halftword
 |-
-| {{mips|SLT}} || Set on Less Than
+| [[SLT - MIPS|SLT]] || Set on Less Than
 |-
-| {{mips|SLTI}} || Set on Less Than Immediate
+| [[SLTI - MIPS|SLTI]] || Set on Less Than Immediate
 |-
-| {{mips|SLTIU}} || Set on Less Than Immediate Unsigned
+| [[SLTIU - MIPS|SLTIU]] || Set on Less Than Immediate Unsigned
 |-
-| {{mips|SLTU}} || Set on Less Than Unsigned
+| [[SLTU - MIPS|SLTU]] || Set on Less Than Unsigned
 |-
-| {{mips|SUB}} || Subtract Word
+| [[SUB - MIPS|SUB]] || Subtract Word
 |-
-| {{mips|SUBU}} || Subtract Unsigned Word
+| [[SUBU - MIPS|SUBU]] || Subtract Unsigned Word
 |}
@@ Line 125: / Line 107: @@
 ! Mnemonic || Description
 |-
-| {{mips|B}} || Unconditional Branch
+| [[B - MIPS|B]] || Unconditional Branch
 |-
-| {{mips|BAL}} || Branch and Link
+| [[BAL - MIPS|BAL]] || Branch and Link
 |-
-| {{mips|BEQ}} || Branch on Equal
+| [[BEQ - MIPS|BEQ]] || Branch on Equal
 |-
-| {{mips|BGEZ}} || Branch on Greater Than or Equal to Zero
+| [[BGEZ - MIPS|BGEZ]] || Branch on Greater Than or Equal to Zero
 |-
-| {{mips|BGEZAL}} || Branch on Greater Than or Equal to Zero and Link
+| [[BGEZAL - MIPS|BGEZAL]] || Branch on Greater Than or Equal to Zero and Link
 |-
-| {{mips|BGTZ}} || Branch on Greater Than Zero
+| [[BGTZ - MIPS|BGTZ]] || Branch on Greater Than Zero
 |-
-| {{mips|BLEZ}} || Branch on Less Than or Equal to Zero
+| [[BLEZ - MIPS|BLEZ]] || Branch on Less Than or Equal to Zero
 |-
-| {{mips|BLTZ}} || Branch on Less Than Zero
+| [[BLTZ - MIPS|BLTZ]] || Branch on Less Than Zero
 |-
-| {{mips|BLTZAL}} || Branch on Less Than Zero and Link
+| [[BLTZAL - MIPS|BLTZAL]] || Branch on Less Than Zero and Link
 |-
-| {{mips|BNE}} || Branch on Not Equal
+| [[BNE - MIPS|BNE]] || Branch on Not Equal
 |-
-| <strike>{{mips|BEQL}}</strike> || Branch on Equal Likely
+| <strike>[[BEQL - MIPS|BEQL]]</strike> || Branch on Equal Likely
 |-
-| <strike>{{mips|BGEZALL}}</strike> || Branch on Greater Than or Equal to Zero and Link Likely
+| <strike>[[BGEZALL - MIPS|BGEZALL]]</strike> || Branch on Greater Than or Equal to Zero and Link Likely
 |-
-| <strike>{{mips|BGEZL}}</strike> || Branch on Greater Than or Equal to Zero Likely
+| <strike>[[BGEZL - MIPS|BGEZL]]</strike> || Branch on Greater Than or Equal to Zero Likely
 |-
-| <strike>{{mips|BGTZL}}</strike> || Branch on Greater Than Zero Likely
+| <strike>[[BGTZL - MIPS|BGTZL]]</strike> || Branch on Greater Than Zero Likely
 |-
-| <strike>{{mips|BLEZL}}</strike> || Branch on Less Than or Equal to Zero Likely
+| <strike>[[BLEZL - MIPS|BLEZL]]</strike> || Branch on Less Than or Equal to Zero Likely
 |-
-| <strike>{{mips|BLTZALL}}</strike> || Branch on Less Than Zero and Link Likely
+| <strike>[[BLTZALL - MIPS|BLTZALL]]</strike> || Branch on Less Than Zero and Link Likely
 |-
-| <strike>{{mips|BLTZL}}</strike> || Branch on Less Than Zero Likely
+| <strike>[[BLTZL - MIPS|BLTZL]]</strike> || Branch on Less Than Zero Likely
 |-
-| <strike>{{mips|BNEL}}</strike> || Branch on Not Equal Likely
+| <strike>[[BNEL - MIPS|BNEL]]</strike> || Branch on Not Equal Likely
 |}
@@ Line 167: / Line 149: @@
 ! Mnemonic || Description
 |-
-| {{mips|J}} || Jump
+| [[J - MIPS|J]] || Jump
 |-
-| {{mips|JAL}} || Jump and Link
+| [[JAL - MIPS|JAL]] || Jump and Link
 |-
-| {{mips|JALR}} || Jump and Link Register
+| [[JALR - MIPS|JALR]] || Jump and Link Register
 |-
 | [[JALR.HB  - MIPS|JALR.HB ]]|| Jump and Link Register with Hazard Barrier
 |-
-| {{mips|JALX}} || Jump and Link Exchange
+| [[JALX - MIPS|JALX]] || Jump and Link Exchange
 |-
-| {{mips|JR}} || Jump Register
+| [[JR - MIPS|JR]] || Jump Register
 |-
-| {{mips|JR.HB}} || Jump Register with Hazard Barrier
+| [[JR.HB - MIPS|JR.HB]] || Jump Register with Hazard Barrier
 |}
@@ Line 186: / Line 168: @@
 ! Mnemonic || Description
 |-
-| {{mips|EHB}} || Execution Hazard Barrier
+| [[EHB - MIPS|EHB]] || Execution Hazard Barrier
 |-
-| {{mips|NOP}} || No Operation
+| [[NOP - MIPS|NOP]] || No Operation
 |-
-| {{mips|PAUSE}} || Wait for LLBit to Clear
+| [[PAUSE - MIPS|PAUSE]] || Wait for LLBit to Clear
 |-
-| {{mips|SSNOP}} || Superscalar No Operation
+| [[SSNOP - MIPS|SSNOP]] || Superscalar No Operation
 |}
@@ Line 199: / Line 181: @@
 ! Mnemonic || Description
 |-
-| {{mips|LB}} ||  Load Byte
+| [[LB - MIPS|LB]] ||  Load Byte
 |-
-| {{mips|LBE}} || Load Byte EVA
+| [[LBE - MIPS|LBE]] || Load Byte EVA
 |-
-| {{mips|LBU}} || Load Byte Unsigned
+| [[LBU - MIPS|LBU]] || Load Byte Unsigned
 |-
-| {{mips|LBUE}} || Load Byte Unsigned EVA
+| [[LBUE - MIPS|LBUE]] || Load Byte Unsigned EVA
 |-
-| {{mips|LH}} || Load Halfword
+| [[LH - MIPS|LH]] || Load Halfword
 |-
-| {{mips|LHE}} || Load Halfword EVA
+| [[LHE - MIPS|LHE]] || Load Halfword EVA
 |-
-| {{mips|LHU}} || Load Halfword Unsigned
+| [[LHU - MIPS|LHU]] || Load Halfword Unsigned
 |-
-| {{mips|LHUE}} || Load Halfword Unsigned EVA
+| [[LHUE - MIPS|LHUE]] || Load Halfword Unsigned EVA
 |-
-| {{mips|LL}} || Load Linked Word
+| [[LL - MIPS|LL]] || Load Linked Word
 |-
-| {{mips|LLE}} || Load Linked Word-EVA
+| [[LLE - MIPS|LLE]] || Load Linked Word-EVA
 |-
-| {{mips|LW}} || Load Word
+| [[LW - MIPS|LW]] || Load Word
 |-
-| {{mips|LWE}} || Load Word EVA
+| [[LWE - MIPS|LWE]] || Load Word EVA
 |-
-| {{mips|LWL}} || Load Word Left
+| [[LWL - MIPS|LWL]] || Load Word Left
 |-
-| {{mips|LWLE}} || Load Word Left EVA
+| [[LWLE - MIPS|LWLE]] || Load Word Left EVA
 |-
-| {{mips|LWR}} || Load Word Right
+| [[LWR - MIPS|LWR]] || Load Word Right
 |-
-| {{mips|LWRE}} || Load Word Right EVA
+| [[LWRE - MIPS|LWRE]] || Load Word Right EVA
 |-
-| {{mips|PREF}} || Prefetch
+| [[PREF - MIPS|PREF]] || Prefetch
 |-
-| {{mips|PREFE}} || Prefetch-EVA
+| [[PREFE - MIPS|PREFE]] || Prefetch-EVA
 |-
-| {{mips|SB}} || Store Byte
+| [[SB - MIPS|SB]] || Store Byte
 |-
-| {{mips|SBE}} || Store Byte EVA
+| [[SBE - MIPS|SBE]] || Store Byte EVA
 |-
-| {{mips|SC}} || Store Conditional Word
+| [[SC - MIPS|SC]] || Store Conditional Word
 |-
-| {{mips|SCE}} || Store Conditional Word EVA
+| [[SCE - MIPS|SCE]] || Store Conditional Word EVA
 |-
-| {{mips|SH}} || Store Halfword
+| [[SH - MIPS|SH]] || Store Halfword
 |-
-| {{mips|SHE}} || Store Halfword EVA
+| [[SHE - MIPS|SHE]] || Store Halfword EVA
 |-
-| {{mips|SW}} || Store Word
+| [[SW - MIPS|SW]] || Store Word
 |-
-| {{mips|SWE}} || Store Word EVA
+| [[SWE - MIPS|SWE]] || Store Word EVA
 |-
-| {{mips|SWL}} || Store Word Left
+| [[SWL - MIPS|SWL]] || Store Word Left
 |-
-| {{mips|SWLE}} || Store Word Left EVA
+| [[SWLE - MIPS|SWLE]] || Store Word Left EVA
 |-
-| {{mips|SWR}} || Store Word Right
+| [[SWR - MIPS|SWR]] || Store Word Right
 |-
-| {{mips|SWRE}} || Store Word Right EVA
+| [[SWRE - MIPS|SWRE]] || Store Word Right EVA
 |-
-| {{mips|SYNC}} || Synchronize Shared Memory
+| [[SYNC - MIPS|SYNC]] || Synchronize Shared Memory
 |-
-| {{mips|SYNCI}} || Synchronize Caches to Make Instruction Writes Effective
+| [[SYNCI - MIPS|SYNCI]] || Synchronize Caches to Make Instruction Writes Effective
 |}
@@ Line 268: / Line 250: @@
 ! Mnemonic || Description
 |-
-| {{mips|AND}} || And
+| [[AND - MIPS|AND]] || And
 |-
-| {{mips|ANDI}} || And Immediate
+| [[ANDI - MIPS|ANDI]] || And Immediate
 |-
-| {{mips|LUI}} || Load Upper Immediate
+| [[LUI - MIPS|LUI]] || Load Upper Immediate
 |-
-| {{mips|NOR}} || Not Or
+| [[NOR - MIPS|NOR]] || Not Or
 |-
-| {{mips|OR}} || Or
+| [[OR - MIPS|OR]] || Or
 |-
-| {{mips|ORI}} || Or Immediate
+| [[ORI - MIPS|ORI]] || Or Immediate
 |-
-| {{mips|XOR}} || Exclusive Or
+| [[XOR - MIPS|XOR]] || Exclusive Or
 |-
-| {{mips|XORI}} || Exclusive Or Immediate
+| [[XORI - MIPS|XORI]] || Exclusive Or Immediate
 |}
@@ Line 289: / Line 271: @@
 ! Mnemonic || Description
 |-
-| {{mips|EXT}} || Extract Bit Field
+| [[EXT - MIPS|EXT]] || Extract Bit Field
 |-
-| {{mips|INS}} || Insert Bit Field
+| [[INS - MIPS|INS]] || Insert Bit Field
 |-
-| {{mips|WSBH}} || Word Swap Bytes Within Halfwords
+| [[WSBH - MIPS|WSBH]] || Word Swap Bytes Within Halfwords
 |}
@@ Line 300: / Line 282: @@
 ! Mnemonic || Description
 |-
-| {{mips|MFHI}} || Move From HI Register
+| [[MFHI - MIPS|MFHI]] || Move From HI Register
 |-
-| {{mips|MFLO}} || Move From LO Register
+| [[MFLO - MIPS|MFLO]] || Move From LO Register
 |-
-| {{mips|MOVF}} || Move Conditional on Floating Point False
+| [[MOVF - MIPS|MOVF]] || Move Conditional on Floating Point False
 |-
-| {{mips|MOVN}} || Move Conditional on Not Zero
+| [[MOVN - MIPS|MOVN]] || Move Conditional on Not Zero
 |-
-| {{mips|MOVT}} || Move Conditional on Floating Point True
+| [[MOVT - MIPS|MOVT]] || Move Conditional on Floating Point True
 |-
-| {{mips|MOVZ}} || Move Conditional on Zero
+| [[MOVZ - MIPS|MOVZ]] || Move Conditional on Zero
 |-
-| {{mips|MTHI}} || Move To HI Register
+| [[MTHI - MIPS|MTHI]] || Move To HI Register
 |-
-| {{mips|MTLO}} || Move To LO Register
+| [[MTLO - MIPS|MTLO]] || Move To LO Register
 |-
-| {{mips|RDHWR}} || Read Hardware Register
+| [[RDHWR - MIPS|RDHWR]] || Read Hardware Register
 |}
@@ Line 323: / Line 305: @@
 ! Mnemonic || Description
 |-
-| {{mips|ROTR}} || Rotate Word Right
+| [[ROTR - MIPS|ROTR]] || Rotate Word Right
 |-
-| {{mips|ROTRV}} || Rotate Word Right Variable
+| [[ROTRV - MIPS|ROTRV]] || Rotate Word Right Variable
 |-
-| {{mips|SLL}} || Shift Word Left Logical
+| [[SLL - MIPS|SLL]] || Shift Word Left Logical
 |-
-| {{mips|SLLV}} || Shift Word Left Logical Variable
+| [[SLLV - MIPS|SLLV]] || Shift Word Left Logical Variable
 |-
-| {{mips|SRA}} || Shift Word Right Arithmetic
+| [[SRA - MIPS|SRA]] || Shift Word Right Arithmetic
 |-
-| {{mips|SRAV}} || Shift Word Right Arithmetic Variable
+| [[SRAV - MIPS|SRAV]] || Shift Word Right Arithmetic Variable
 |-
-| {{mips|SRL}} || Shift Word Right Logical
+| [[SRL - MIPS|SRL]] || Shift Word Right Logical
 |-
-| {{mips|SRLV}} || Shift Word Right Logical Variable
+| [[SRLV - MIPS|SRLV]] || Shift Word Right Logical Variable
 |}
@@ Line 344: / Line 326: @@
 ! Mnemonic || Description
 |-
-| {{mips|BREAK}} || Breakpoint
+| [[BREAK - MIPS|BREAK]] || Breakpoint
 |-
-| {{mips|SYSCALL}} || System Call
+| [[SYSCALL - MIPS|SYSCALL]] || System Call
 |-
-| {{mips|TEQ}} || Trap if Equal
+| [[TEQ - MIPS|TEQ]] || Trap if Equal
 |-
-| {{mips|TEQI}} || Trap if Equal Immediate
+| [[TEQI - MIPS|TEQI]] || Trap if Equal Immediate
 |-
-| {{mips|TGE}} || Trap if Greater or Equal
+| [[TGE - MIPS|TGE]] || Trap if Greater or Equal
 |-
-| {{mips|TGEI}} || Trap if Greater of Equal Immediate
+| [[TGEI - MIPS|TGEI]] || Trap if Greater of Equal Immediate
 |-
-| {{mips|TGEIU}} || Trap if Greater or Equal Immediate Unsigned
+| [[TGEIU - MIPS|TGEIU]] || Trap if Greater or Equal Immediate Unsigned
 |-
-| {{mips|TGEU}} || Trap if Greater or Equal Unsigned
+| [[TGEU - MIPS|TGEU]] || Trap if Greater or Equal Unsigned
 |-
-| {{mips|TLT}} || Trap if Less Than
+| [[TLT - MIPS|TLT]] || Trap if Less Than
 |-
-| {{mips|TLTI}} || Trap if Less Than Immediate
+| [[TLTI - MIPS|TLTI]] || Trap if Less Than Immediate
 |-
-| {{mips|TLTIU}} || Trap if Less Than Immediate Unsigned
+| [[TLTIU - MIPS|TLTIU]] || Trap if Less Than Immediate Unsigned
 |-
-| {{mips|TLTU}} || Trap if Less Than Unsigned
+| [[TLTU - MIPS|TLTU]] || Trap if Less Than Unsigned
 |-
-| {{mips|TNE}} || Trap if Not Equal
+| [[TNE - MIPS|TNE]] || Trap if Not Equal
 |-
-| {{mips|TNEI}} || Trap if Not Equal Immediate
+| [[TNEI - MIPS|TNEI]] || Trap if Not Equal Immediate
 |}
@@ Line 380: / Line 362: @@
 ! Mnemonic || Description
 |-
-| {{mips|ABS.fmt}} || Floating Point Absolute Value
+| [[ABS.fmt - MIPS|ABS.fmt]] || Floating Point Absolute Value
 |-
-| {{mips|ADD.fmt}} || Floating Point Add
+| [[ADD.fmt - MIPS|ADD.fmt]] || Floating Point Add
 |-
-| {{mips|DIV.fmt}} || Floating Point Divide
+| [[DIV.fmt - MIPS|DIV.fmt]] || Floating Point Divide
 |-
-| {{mips|MADD.fmt}} || Floating Point Multiply Add
+| [[MADD.fmt - MIPS|MADD.fmt]] || Floating Point Multiply Add
 |-
-| {{mips|MSUB.fmt}} || Floating Point Multiply Subtract
+| [[MSUB.fmt - MIPS|MSUB.fmt]] || Floating Point Multiply Subtract
 |-
-| {{mips|MUL.fmt}} || Floating Point Multiply
+| [[MUL.fmt - MIPS|MUL.fmt]] || Floating Point Multiply
 |-
-| {{mips|NEG.fmt}} || Floating Point Negate
+| [[NEG.fmt - MIPS|NEG.fmt]] || Floating Point Negate
 |-
-| {{mips|NMADD.fmt}} || Floating Point Negative Multiply Add
+| [[NMADD.fmt - MIPS|NMADD.fmt]] || Floating Point Negative Multiply Add
 |-
-| {{mips|NMSUB.fmt}} || Floating Point Negative Multiply Subtract
+| [[NMSUB.fmt - MIPS|NMSUB.fmt]] || Floating Point Negative Multiply Subtract
 |-
-| {{mips|RECIP.fmt}} || Reciprocal Approximation
+| [[RECIP.fmt - MIPS|RECIP.fmt]] || Reciprocal Approximation
 |-
-| {{mips|RSQRT.fmt}} || Reciprocal Square Root Approximation
+| [[RSQRT.fmt - MIPS|RSQRT.fmt]] || Reciprocal Square Root Approximation
 |-
-| {{mips|SQRT.fmt}} || Floating Point Square Root
+| [[SQRT.fmt - MIPS|SQRT.fmt]] || Floating Point Square Root
 |-
-| {{mips|SUB.fmt}} || Floating Point Subtract
+| [[SUB.fmt - MIPS|SUB.fmt]] || Floating Point Subtract
 |}
@@ Line 412: / Line 394: @@
 ! Mnemonic || Description
 |-
-| {{mips|BC1F}} || Branch on FP False
+| [[BC1F - MIPS|BC1F]] || Branch on FP False
 |-
-| {{mips|BC1T}} || Branch on FP True
+| [[BC1T - MIPS|BC1T]] || Branch on FP True
 |-
-| <strike>{{mips|BC1FL}}</strike> || Branch on FP False Likely
+| <strike>[[BC1FL - MIPS|BC1FL]]</strike> || Branch on FP False Likely
 |-
-| <strike>{{mips|BC1TL}}</strike> || Branch on FP True Likely
+| <strike>[[BC1TL - MIPS|BC1TL]]</strike> || Branch on FP True Likely
 |}
@@ Line 425: / Line 407: @@
 ! Mnemonic || Description
 |-
-| {{mips|C.cond.fmt}} || Floating Point Compare
+| [[C.cond.fmt - MIPS|C.cond.fmt]] || Floating Point Compare
 |}
@@ Line 432: / Line 414: @@
 ! Mnemonic || Description
 |-
-| {{mips|ALNV.PS}} || Floating Point Align Variable
+| [[ALNV.PS - MIPS|ALNV.PS]] || Floating Point Align Variable
 |-
-| {{mips|CEIL.L.fmt}} || Floating Point Ceiling Convert to Long Fixed Point
+| [[CEIL.L.fmt - MIPS|CEIL.L.fmt]] || Floating Point Ceiling Convert to Long Fixed Point
 |-
-| {{mips|CEIL.W.fmt}} || Floating Point Ceiling Convert to Word Fixed Point
+| [[CEIL.W.fmt - MIPS|CEIL.W.fmt]] || Floating Point Ceiling Convert to Word Fixed Point
 |-
-| {{mips|CVT.D.fmt}} || Floating Point Convert to Double Floating Point
+| [[CVT.D.fmt - MIPS|CVT.D.fmt]] || Floating Point Convert to Double Floating Point
 |-
-| {{mips|CVT.L.fmt}} || Floating Point Convert to Long Fixed Point
+| [[CVT.L.fmt - MIPS|CVT.L.fmt]] || Floating Point Convert to Long Fixed Point
 |-
-| {{mips|CVT.PS.S}} || Floating Point Convert Pair to Paired Single
+| [[CVT.PS.S - MIPS|CVT.PS.S]] || Floating Point Convert Pair to Paired Single
 |-
-| {{mips|CVT.S.PL}} || Floating Point Convert Pair Lower to Single Floating Point
+| [[CVT.S.PL - MIPS|CVT.S.PL]] || Floating Point Convert Pair Lower to Single Floating Point
 |-
-| {{mips|CVT.S.PU}} || Floating Point Convert Pair Upper to Single Floating Point
+| [[CVT.S.PU - MIPS|CVT.S.PU]] || Floating Point Convert Pair Upper to Single Floating Point
 |-
-| {{mips|CVT.S.fmt}} || Floating Point Convert to Single Floating Point
+| [[CVT.S.fmt - MIPS|CVT.S.fmt]] || Floating Point Convert to Single Floating Point
 |-
-| {{mips|CVT.W.fmt}} || Floating Point Convert to Word Fixed Point
+| [[CVT.W.fmt - MIPS|CVT.W.fmt]] || Floating Point Convert to Word Fixed Point
 |-
-| {{mips|FLOOR.L.fmt}} || Floating Point Floor Convert to Long Fixed Point
+| [[FLOOR.L.fmt - MIPS|FLOOR.L.fmt]] || Floating Point Floor Convert to Long Fixed Point
 |-
-| {{mips|FLOOR.W.fmt}} || Floating Point Floor Convert to Word Fixed Point
+| [[FLOOR.W.fmt - MIPS|FLOOR.W.fmt]] || Floating Point Floor Convert to Word Fixed Point
 |-
-| {{mips|PLL.PS}} || Pair Lower Lower
+| [[PLL.PS - MIPS|PLL.PS]] || Pair Lower Lower
 |-
-| {{mips|PLU.PS}} || Pair Lower Upper
+| [[PLU.PS - MIPS|PLU.PS]] || Pair Lower Upper
 |-
-| {{mips|PUL.PS}} || Pair Upper Lower
+| [[PUL.PS - MIPS|PUL.PS]] || Pair Upper Lower
 |-
-| {{mips|PUU.PS}} || Pair Upper Upper
+| [[PUU.PS - MIPS|PUU.PS]] || Pair Upper Upper
 |-
-| {{mips|ROUND.L.fmt}} || Floating Point Round to Long Fixed Point
+| [[ROUND.L.fmt - MIPS|ROUND.L.fmt]] || Floating Point Round to Long Fixed Point
 |-
-| {{mips|ROUND.W.fmt}} || Floating Point Round to Word Fixed Point
+| [[ROUND.W.fmt - MIPS|ROUND.W.fmt]] || Floating Point Round to Word Fixed Point
 |-
-| {{mips|TRUNC.L.fmt}} || Floating Point Truncate to Long Fixed Point
+| [[TRUNC.L.fmt - MIPS|TRUNC.L.fmt]] || Floating Point Truncate to Long Fixed Point
 |-
-| {{mips|TRUNC.W.fmt}} || Floating Point Truncate to Word Fixed Point
+| [[TRUNC.W.fmt - MIPS|TRUNC.W.fmt]] || Floating Point Truncate to Word Fixed Point
 |}
@@ Line 478: / Line 460: @@
 ! Mnemonic || Description
 |-
-| {{mips|LDC1}} || Load Doubleword to Floating Point
+| [[LDC1 - MIPS|LDC1]] || Load Doubleword to Floating Point
 |-
-| {{mips|LDXC1}} || Load Doubleword Indexed to Floating Point
+| [[LDXC1 - MIPS|LDXC1]] || Load Doubleword Indexed to Floating Point
 |-
-| {{mips|LUXC1}} || Load Doubleword Indexed Unaligned to Floating Point
+| [[LUXC1 - MIPS|LUXC1]] || Load Doubleword Indexed Unaligned to Floating Point
 |-
-| {{mips|LWC1}} || Load Word to Floating Point
+| [[LWC1 - MIPS|LWC1]] || Load Word to Floating Point
 |-
-| {{mips|LWXC1}} || Load Word Indexed to Floating Point
+| [[LWXC1 - MIPS|LWXC1]] || Load Word Indexed to Floating Point
 |-
-| {{mips|PREFX}} || Prefetch Indexed
+| [[PREFX - MIPS|PREFX]] || Prefetch Indexed
 |-
-| {{mips|SDC1}} || Store Doubleword from Floating Point
+| [[SDC1 - MIPS|SDC1]] || Store Doubleword from Floating Point
 |-
-| {{mips|SDXC1}} || Store Doubleword Indexed from Floating Point
+| [[SDXC1 - MIPS|SDXC1]] || Store Doubleword Indexed from Floating Point
 |-
-| {{mips|SUXC1}} || Store Doubleword Indexed Unaligned from Floating Point
+| [[SUXC1 - MIPS|SUXC1]] || Store Doubleword Indexed Unaligned from Floating Point
 |-
-| {{mips|SWC1}} || Store Word from Floating Point
+| [[SWC1 - MIPS|SWC1]] || Store Word from Floating Point
 |-
-| {{mips|SWXC1}} || Store Word Indexed from Floating Point
+| [[SWXC1 - MIPS|SWXC1]] || Store Word Indexed from Floating Point
 |}
@@ Line 506: / Line 488: @@
 ! Mnemonic || Description
 |-
-| {{mips|CFC1}} || Move Control Word from Floating Point
+| [[CFC1 - MIPS|CFC1]] || Move Control Word from Floating Point
 |-
-| {{mips|CTC1}} || Move Control Word to Floating Point
+| [[CTC1 - MIPS|CTC1]] || Move Control Word to Floating Point
 |-
-| {{mips|MFC1}} || Move Word from Floating Point
+| [[MFC1 - MIPS|MFC1]] || Move Word from Floating Point
 |-
-| {{mips|MFHC1}} || Move Word from High Half of Floating Point Register
+| [[MFHC1 - MIPS|MFHC1]] || Move Word from High Half of Floating Point Register
 |-
-| {{mips|MOV.fmt}} || Floating Point Move
+| [[MOV.fmt - MIPS|MOV.fmt]] || Floating Point Move
 |-
-| {{mips|MOVF.fmt}} || Floating Point Move Conditional on Floating Point False
+| [[MOVF.fmt - MIPS|MOVF.fmt]] || Floating Point Move Conditional on Floating Point False
 |-
-| {{mips|MOVN.fmt}} || Floating Point Move Conditional on Not Zero
+| [[MOVN.fmt - MIPS|MOVN.fmt]] || Floating Point Move Conditional on Not Zero
 |-
-| {{mips|MOVT.fmt}} || Floating Point Move Conditional on Floating Point True
+| [[MOVT.fmt - MIPS|MOVT.fmt]] || Floating Point Move Conditional on Floating Point True
 |-
-| {{mips|MOVZ.fmt}} || Floating Point Move Conditional on Zero
+| [[MOVZ.fmt - MIPS|MOVZ.fmt]] || Floating Point Move Conditional on Zero
 |-
-| {{mips|MTC1}} || Move Word to Floating Point
+| [[MTC1 - MIPS|MTC1]] || Move Word to Floating Point
 |-
-| {{mips|MTHC1}} || Move Word to High Half of Floating Point Register
+| [[MTHC1 - MIPS|MTHC1]] || Move Word to High Half of Floating Point Register
 |}
@@ Line 535: / Line 517: @@
 ! Mnemonic || Description
 |-
-| {{mips|BC2F}} || Branch on COP2 False
+| [[BC2F - MIPS|BC2F]] || Branch on COP2 False
 |-
-| {{mips|BC2T}} || Branch on COP2 True
+| [[BC2T - MIPS|BC2T]] || Branch on COP2 True
 |-
-| <strike>{{mips|BC2FL}}</strike> || Branch on COP2 False Likely
+| <strike>[[BC2FL - MIPS|BC2FL]]</strike> || Branch on COP2 False Likely
 |-
-| <strike>{{mips|BC2TL}}</strike> || Branch on COP2 True Likely
+| <strike>[[BC2TL - MIPS|BC2TL]]</strike> || Branch on COP2 True Likely
 |}
@@ Line 549: / Line 531: @@
 ! Mnemonic || Description
 |-
-| {{mips|COP2}} || Coprocessor Operation to Coprocessor 2
+| [[COP2 - MIPS|COP2]] || Coprocessor Operation to Coprocessor 2
 |}
@@ Line 556: / Line 538: @@
 ! Mnemonic || Description
 |-
-| {{mips|DC2}} || Load Doubleword to Coprocessor 2
+| [[DC2 - MIPS|DC2]] || Load Doubleword to Coprocessor 2
 |-
-| {{mips|LWC2}} || Load Word to Coprocessor 2
+| [[LWC2 - MIPS|LWC2]] || Load Word to Coprocessor 2
 |-
-| {{mips|SDC2}} || Store Doubleword from Coprocessor 2
+| [[SDC2 - MIPS|SDC2]] || Store Doubleword from Coprocessor 2
 |-
-| {{mips|SWC2}} || Store Word from Coprocessor 2
+| [[SWC2 - MIPS|SWC2]] || Store Word from Coprocessor 2
 |}
@@ Line 570: / Line 552: @@
 ! Mnemonic || Description
 |-
-| {{mips|CFC2}} || Move Control Word from Coprocessor 2
+| [[CFC2 - MIPS|CFC2]] || Move Control Word from Coprocessor 2
 |-
-| {{mips|CTC2}} || Move Control Word to Coprocessor 2
+| [[CTC2 - MIPS|CTC2]] || Move Control Word to Coprocessor 2
 |-
-| {{mips|MFC2}} || Move Word from Coprocessor 2
+| [[MFC2 - MIPS|MFC2]] || Move Word from Coprocessor 2
 |-
-| {{mips|MFHC2}} || Move Word from High Half of Coprocessor 2 Register
+| [[MFHC2 - MIPS|MFHC2]] || Move Word from High Half of Coprocessor 2 Register
 |-
-| {{mips|MTC2}} || Move Word to Coprocessor 2
+| [[MTC2 - MIPS|MTC2]] || Move Word to Coprocessor 2
 |-
-| {{mips|MTHC2}} || Move Word to High Half of Coprocessor 2 Register
+| [[MTHC2 - MIPS|MTHC2]] || Move Word to High Half of Coprocessor 2 Register
 |}
@@ Line 588: / Line 570: @@
 ! Mnemonic || Description
 |-
-| {{mips|CACHE}} || Perform Cache Operation
+| [[CACHE - MIPS|CACHE]] || Perform Cache Operation
 |-
-| {{mips|CACHEE}} || Perform Cache Operation EVA
+| [[CACHEE - MIPS|CACHEE]] || Perform Cache Operation EVA
 |-
-| {{mips|DI}} || Disable Interrupts
+| [[DI - MIPS|DI]] || Disable Interrupts
 |-
-| {{mips|EI}} || Enable Interrupts
+| [[EI - MIPS|EI]] || Enable Interrupts
 |-
-| {{mips|ERET}} || Exception Return
+| [[ERET - MIPS|ERET]] || Exception Return
 |-
-| {{mips|MFC0}} || Move from {{mips|Coprocessor 0}}
+| [[MFC0 - MIPS|MFC0]] || Move from Coprocessor 0
 |-
-| {{mips|MTC0}} || Move to {{mips|Coprocessor 0}}
+| [[MTC0 - MIPS|MTC0]] || Move to Coprocessor 0
 |-
-| {{mips|RDPGPR}} || Read GPR from Previous Shadow Set
+| [[RDPGPR - MIPS|RDPGPR]] || Read GPR from Previous Shadow Set
 |-
-| {{mips|TLBP}} || Probe TLB for Matching Entry
+| [[TLBP - MIPS|TLBP]] || Probe TLB for Matching Entry
 |-
-| {{mips|TLBR}} || Read Indexed TLB Entry
+| [[TLBR - MIPS|TLBR]] || Read Indexed TLB Entry
 |-
-| {{mips|TLBWI}} || Write Indexed TLB Entry
+| [[TLBWI - MIPS|TLBWI]] || Write Indexed TLB Entry
 |-
-| {{mips|TLBWR}} || Write Random TLB Entry
+| [[TLBWR - MIPS|TLBWR]] || Write Random TLB Entry
 |-
-| {{mips|WAIT}} || Enter Standby Mode
+| [[WAIT - MIPS|WAIT]] || Enter Standby Mode
 |-
-| {{mips|WRPGPR}} || Write GPR to Previous Shadow Set
+| [[WRPGPR - MIPS|WRPGPR]] || Write GPR to Previous Shadow Set
 |}
@@ Line 621: / Line 603: @@
 ! Mnemonic || Description
 |-
-| {{mips|DERET}} ||Debug Exception Return
+| [[DERET - MIPS|DERET]] ||Debug Exception Return
 |-
-| {{mips|SDBBP}} || Software Debug Breakpoint
+| [[SDBBP - MIPS|SDBBP]] || Software Debug Breakpoint
 |}
-== References ==
-{{reflist|30em}}
 [[Category:Assembly language]]