From WikiChip
Difference between revisions of "mediatek/helio/p30"
< mediatek‎ | helio

(Memory controller)
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|bandwidth dchan=11.92 GiB/s
 
|bandwidth dchan=11.92 GiB/s
 
}}
 
}}
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== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Mali-G71
 +
| device id          =
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| designer            = ARM Holdings
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| execution units    = 2
 +
| frequency          = 950 MHz
 +
 +
| output dsi          = Yes
 +
 +
| max res dsi        = 2160x1080
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| direct3d ver        = 12
 +
| opencl ver          = 2.0
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| opengl ver          = 3.2
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| opengl es ver      = 3.2
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| vulkan ver          = 1.0
 +
| openvg ver          = 1.1
 +
}}
 +
 +
* Hardware Acceleration:
 +
** Encode: [[H.264]], VP9 @ 30 FPS
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** Decode: H.264, [[H.265]] / HEVC, VP9 @ 30 FPS
 +
 +
== Wireless ==
 +
{{wireless links
 +
| 4g                = Yes
 +
| lte a            = Yes
 +
| e-utran          = Yes
 +
| ue cat            = 7 (DL), 13 (UL)
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}}
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== Camera ==
 +
* 25MP (single), 16MP+16MP (dual)
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** 3840 x 2160 max recording resolution @ 30 FPS
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** color+mono, wide+tele zoom with real-time depth engine
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== Utilizing devices ==
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<!--
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* [[used by::XXXXXXXXXXX]]
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-->
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{{expand list}}

Revision as of 14:54, 10 September 2017

Template:mpu Helio P30 is a mid-range performance 64-bit octa-core ARM LTE system on a chip designed by MediaTek set to launch in late 2017. This SoC, which is fabricated on TSMC's 16 nm process, incorporates eight Cortex-A53 cores with four little cores operating at up to 1.65 GHz and four big cores operating at up to 2.3 GHz. The Helio P30 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting LTE User Equipment (UE) category 7 (DL)/13 (UL).


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3200
Supports ECCNo
Max Mem6 GiB
Controllers1
Channels2
Width16 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G71
DesignerARM Holdings
Execution Units2
Frequency950 MHz
0.95 GHz
950,000 KHz
OutputDSI

Max Resolution
DSI2160x1080

Standards
Direct3D12
OpenGL3.2
OpenCL2.0
OpenGL ES3.2
OpenVG1.1
Vulkan1.0
  • Hardware Acceleration:
    • Encode: H.264, VP9 @ 30 FPS
    • Decode: H.264, H.265 / HEVC, VP9 @ 30 FPS

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
E-UTRANYes
UE Cat7 (DL), 13 (UL)

Camera

  • 25MP (single), 16MP+16MP (dual)
    • 3840 x 2160 max recording resolution @ 30 FPS
    • color+mono, wide+tele zoom with real-time depth engine

Utilizing devices

This list is incomplete; you can help by expanding it.