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== Relation to PPA ==
 
== Relation to PPA ==
 
{{main|power-performance-area|l1=Power-Performance-Area (PPA)}}
 
{{main|power-performance-area|l1=Power-Performance-Area (PPA)}}
[[File:n16 vs n28 ppa.png|right|200px|thumb|TSMC N16 vs N28 PPA in terms of iso-speed and iso-power at a certain nominal point.]]
 
 
Iso-comparison plays an important role in the advertised benefits of new [[process nodes]]. When a foundry announces a new technology node, the [[Power-Performance-Area]] (PPA) benefits of this node is usually given in terms of ''iso-power'' and ''iso-performance'' in order to demonstrate the raw capabilities of the underlying transistors. For example, [[TSMC]]'s [[N16|16-nanometer FinFET]] process was said to deliver 2x the logic density along with >35% speed gain at iso-power OR >55% lower power at iso-speed over TSMC's own [[28 nm process]]. In other words, TSMC claims that, compared to their [[28 nm process]], their [[N16|16 nm process]] can deliver over 35% speed gain at the same total power consumption, or alternatively, over 55% power reduction at the same speed. The [[figure of merits]] (FOMs) used by TSMC for those values consisted of some combination of RO inverters, NAND, and NOT gates with Fan-Out 3 (FO3). It's worth noting that while TSMC highlights the two extreme points of its process node, realistically, chip designs choose a better sweet-spot in between those two extremes.
 
Iso-comparison plays an important role in the advertised benefits of new [[process nodes]]. When a foundry announces a new technology node, the [[Power-Performance-Area]] (PPA) benefits of this node is usually given in terms of ''iso-power'' and ''iso-performance'' in order to demonstrate the raw capabilities of the underlying transistors. For example, [[TSMC]]'s [[N16|16-nanometer FinFET]] process was said to deliver 2x the logic density along with >35% speed gain at iso-power OR >55% lower power at iso-speed over TSMC's own [[28 nm process]]. In other words, TSMC claims that, compared to their [[28 nm process]], their [[N16|16 nm process]] can deliver over 35% speed gain at the same total power consumption, or alternatively, over 55% power reduction at the same speed. The [[figure of merits]] (FOMs) used by TSMC for those values consisted of some combination of RO inverters, NAND, and NOT gates with Fan-Out 3 (FO3). It's worth noting that while TSMC highlights the two extreme points of its process node, realistically, chip designs choose a better sweet-spot in between those two extremes.
  
 
== See also ==
 
== See also ==
 
* [[PPA]]
 
* [[PPA]]

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