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When the inverter's input is HIGH and the output is LOW, all the energy stored in the load capacitor is dissipated in the nMOS device because during that time the pMOS is cut off and the nMOS device is conducting. Therefore the energy dissipated in the nMOS device can be expressed as \( E_n = \frac{1}{2}C_LV_{DD}^2 \). During one complete switch cycle the total energy is the sum of both transistors: \( E_T = E_p + E_n = \frac{1}{2}C_LV_{DD}^2 + \frac{1}{2}C_LV_{DD}^2 = C_LV_{DD}^2 \). The power dissipated in terms of [[frequency]] can be expressed as \( E_T = P \centerdot t \); \( P = \frac{E_T}{t} \); \( P = fE_T \); \( P = fC_LV_{DD}^2 \). Which shows that the switching frequency and \( V_{DD}^2 \) are directly proportional to the [[power dissipation]] of a CMOS inverter. The dynamic capacitive power is \( P_{dyn} = C_LV_{DD}^2f \). | When the inverter's input is HIGH and the output is LOW, all the energy stored in the load capacitor is dissipated in the nMOS device because during that time the pMOS is cut off and the nMOS device is conducting. Therefore the energy dissipated in the nMOS device can be expressed as \( E_n = \frac{1}{2}C_LV_{DD}^2 \). During one complete switch cycle the total energy is the sum of both transistors: \( E_T = E_p + E_n = \frac{1}{2}C_LV_{DD}^2 + \frac{1}{2}C_LV_{DD}^2 = C_LV_{DD}^2 \). The power dissipated in terms of [[frequency]] can be expressed as \( E_T = P \centerdot t \); \( P = \frac{E_T}{t} \); \( P = fE_T \); \( P = fC_LV_{DD}^2 \). Which shows that the switching frequency and \( V_{DD}^2 \) are directly proportional to the [[power dissipation]] of a CMOS inverter. The dynamic capacitive power is \( P_{dyn} = C_LV_{DD}^2f \). | ||
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== Discrete chips == | == Discrete chips == |