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Difference between revisions of "intel/xeon e5/e5-4655 v4"
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{{intel title|Xeon E5-4655 v4}}
 
{{intel title|Xeon E5-4655 v4}}
 
{{chip
 
{{chip
−
| name               = Xeon E5-4655 v4
+
|name=Xeon E5-4655 v4
−
| no image           = Yes
+
|no image=Yes
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =
+
|model number=E5-4655 v4
−
| designer           = Intel
+
|part number=CM8066002065000
−
| manufacturer       = Intel
+
|s-spec=SR2SH
−
| model number       = E5-4655 v4
+
|s-spec qs=QKSX
−
| part number         = CM8066002065000
+
|market=Server
−
| part number 2      =  
+
|first announced=June 20, 2016
−
| part number 3      =
+
|first launched=June 20, 2016
−
| part number 4      =  
+
|release price=$4616
−
| market             = Server
+
|family=Xeon E5
−
| first announced     = June 20, 2016
+
|series=E5-4000
−
| first launched     = June 20, 2016
+
|locked=Yes
−
| last order          =
+
|frequency=2,500 MHz
−
| last shipment      =
+
|turbo frequency1=3,200 MHz
−
| release price       = $4616
+
|turbo frequency2=3,200 MHz
−
 
+
|turbo frequency3=3,000 MHz
−
| family             = Xeon E5
+
|turbo frequency4=2,900 MHz
−
| series             = E5-4000
+
|turbo frequency5=2,800 MHz
−
| locked             = Yes
+
|turbo frequency6=2,700 MHz
−
| frequency           = 2,500 MHz
+
|turbo frequency7=2,600 MHz
−
| turbo frequency    = Yes
+
|turbo frequency8=2,600 MHz
−
| turbo frequency1    = 3,200 MHz
+
|turbo frequency=Yes
−
| turbo frequency2    =  
+
|bus type=QPI
−
| bus type           = QPI
+
|bus speed=4,800 MHz
−
| bus speed           = 4,800 MHz
+
|bus links=2
−
| bus rate           = 9.6 GT/s
+
|bus rate=9.6 GT/s
−
| bus links          = 2
+
|clock multiplier=25
−
| clock multiplier   = 25
+
|cpuid=406F1
−
| s-spec              = SR2SH
+
|isa=x86-64
−
| s-spec es          =
+
|isa family=x86
−
| s-spec qs          = QKSX
+
|microarch=Broadwell
−
| cpuid               = 406F1
+
|platform=Grantley EP 4S
−
 
+
|chipset=C610 Series
−
| isa family          = x86
+
|core name=Broadwell EP
−
| isa                 = x86-64
+
|core family=6
−
| microarch           = Broadwell
+
|core model=4F
−
| platform           = Grantley EP 4S
+
|core stepping=M0
−
| chipset             = C610 Series
+
|process=14 nm
−
| core name           = Broadwell EP
+
|transistors=3,200,000,000
−
| core family         = 6
+
|technology=CMOS
−
| core model         = 4F
+
|word size=64 bit
−
| core stepping       = M0
+
|core count=8
−
| process             = 14 nm
+
|thread count=16
−
| transistors         = 3,200,000,000
+
|max memory=1,536 GiB
−
| technology         = CMOS
+
|max cpus=4
−
| die size            = 246.24 mm²
+
|v core=1.82 V
−
| word size           = 64 bit
+
|v io=1.2 V
−
| core count         = 8
+
|v io tolerance=3%
−
| thread count       = 16
+
|tdp=135 W
−
| max cpus            = 4
+
|tcase min=0 °C
−
| max memory         = 1,536 GiB
+
|tcase max=82 °C
−
 
+
|tstorage min=-25 °C
−
 
+
|tstorage max=125 °C
−
| v core             = 1.82 V
+
|die size=246.24 mm²
−
| v core tolerance    =
+
|packaging=Yes
−
| v io               = 1.2 V
+
|package 0=FCLGA-2011-v3
−
| v io tolerance     = 3%
+
|package 0 type=FCLGA
−
| sdp                =
+
|package 0 pins=2011
−
| tdp                 = 135 W
+
|package 0 pitch=0.8814 mm
−
| ctdp down          =
+
|package 0 width=52.5 mm
−
| ctdp down frequency =
+
|package 0 length=45.0 mm
−
| ctdp up            =
+
|package 0 height=5.316 mm
−
| ctdp up frequency  =
+
|socket 0=LGA-2011-v3
−
| tjunc min          =
+
|socket 0 type=LGA
−
| tjunc max          =
 
−
| tcase min           = 0 °C
 
−
| tcase max           = 82 °C
 
−
| tstorage min       = -25 °C
 
−
| tstorage max       = 125 °C
 
−
 
 
−
| packaging           = Yes
 
−
| package 0           = FCLGA-2011-v3
 
−
| package 0 type     = FCLGA
 
−
| package 0 pins     = 2011
 
−
| package 0 pitch     = 0.8814 mm
 
−
| package 0 width     = 52.5 mm
 
−
| package 0 length   = 45.0 mm
 
−
| package 0 height   = 5.316 mm
 
−
| socket 0           = LGA-2011-v3
 
−
| socket 0 type       = LGA
 
 
}}
 
}}
 
The '''Xeon E5-4655 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-4655 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).

Latest revision as of 17:26, 31 January 2024

Edit Values
Xeon E5-4655 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-4655 v4
Part NumberCM8066002065000
S-SpecSR2SH
QKSX (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$4616
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-4000
LockedYes
Frequency2,500 MHz
Turbo FrequencyYes
Turbo Frequency3,200 MHz (1 core),
3,200 MHz (2 cores),
3,000 MHz (3 cores),
2,900 MHz (4 cores),
2,800 MHz (5 cores),
2,700 MHz (6 cores),
2,600 MHz (7 cores),
2,600 MHz (8 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier25
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 4S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores8
Threads16
Max Memory1,536 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP135 W
Tcase0 °C – 82 °C
Tstorage-25 °C – 125 °C

The Xeon E5-4655 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8x256 KiB 8-way set associative (per core, write-back)
L3$ 30 MiB
30,720 KiB
31,457,280 B
0.0293 GiB
8x3.75 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-4655_v4&oldid=102183"
Facts about "Xeon E5-4655 v4 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-4655 v4 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +
max pcie lanes40 +