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{{intel title|Xeon E5-2696 v4}}
 
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== Expansions ==
 
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Latest revision as of 16:28, 13 December 2017

Edit Values
Xeon E5-2696 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2696 v4
Part NumberCM8066002402501
S-SpecSR2J0
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,200 MHz
Turbo FrequencyYes
Turbo Frequency3,700 MHz (1 core),
3,700 MHz (2 cores),
3,500 MHz (3 cores),
3,400 MHz (4 cores),
3,300 MHz (5 cores),
3,200 MHz (6 cores),
3,100 MHz (7 cores),
3,000 MHz (8 cores),
2,900 MHz (9 cores),
2,800 MHz (10 cores),
2,800 MHz (11 cores),
2,800 MHz (12 cores),
2,800 MHz (13 cores),
2,800 MHz (14 cores),
2,800 MHz (15 cores),
2,800 MHz (16 cores),
2,800 MHz (17 cores),
2,800 MHz (18 cores),
2,800 MHz (19 cores),
2,800 MHz (20 cores),
2,800 MHz (21 cores),
2,800 MHz (22 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier22
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingB0
Process14 nm
Transistors7,200,000,000
TechnologyCMOS
Die456.12 mm²
Word Size64 bit
Cores22
Threads44
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP150 W
Tcase0 °C – ? °C
Tstorage-25 °C – 125 °C

The Xeon E5-2696 v4 is a 64-bit docosa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S environments. Operating at 2.2 GHz with a turbo boost frequency of 3.7 GHz for a single active core, this MPU has a TDP of 150 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L1D$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L2$ 5.5 MiB
5,632 KiB
5,767,168 B
0.00537 GiB
22x256 KiB 8-way set associative (per core, write-back)
L3$ 55 MiB
56,320 KiB
57,671,680 B
0.0537 GiB
22x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2696_v4&oldid=71008"
Facts about "Xeon E5-2696 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description8-way set associative +
l2$ size5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) +
l3$ description20-way set associative +
l3$ size55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) +