Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon d/d-1571"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
m (Bot: replacing deprecated (and now obselete) {{mpu features}} with {{x86 features}}) |
||
| Line 139: | Line 139: | ||
== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes | ||
Revision as of 15:47, 13 December 2017
Template:mpu The Xeon D-1571 is a 64-bit hexadeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1571 operates at 1.3 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).
Cache
- Main article: Broadwell § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 512 KiB 524,288 B 0.5 MiB |
16x32 KiB 8-way set associative (per core) |
| L1D$ | 512 KiB 524,288 B 0.5 MiB |
16x32 KiB 8-way set associative (per core) |
| L2$ | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB |
16x256 KiB 8-way set associative (per core) |
| L3$ | 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB |
16x1.5 MiB (per core) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max memory | 128 GiB |
Expansions
Networking
| Networking | |
| SFI interface | Yes |
| KR interface | Yes |
| KR4 interface | No |
| KX interface | Yes |
| KX4 interface | No |
| 10Base-T | No |
| 100Base-T | No |
| 1000Base-T | Yes |
| 10GBase-T | Yes |
Features
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||
Facts about "Xeon D-1571 - Intel"
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology + and Transactional Synchronization Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
