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Difference between revisions of "intel/xeon d/d-1531"
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Revision as of 06:48, 23 June 2017

Template:mpu The Xeon D-1531 is a 64-bit hexa-core x86-64 microserver SoC that was introduced by Intel in November of 2015. The D-1531 operates at 2.2 GHz with a turbo frequency of 2.7 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core)
L1D$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core)
L2$ 1,536 KiB
1.5 MiB
1,572,864 B
0.00146 GiB
6x256 KiB 8-way set associative (per core)
L3$ 9 MiB
9,216 KiB
9,437,184 B
0.00879 GiB
6x1.5 MiB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max memory 128 GiB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface Yes
KR interface Yes
KR4 interface No
KX interface Yes
KX4 interface No
10Base-T No
100Base-T No
1000Base-T Yes
10GBase-T Yes

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1531&oldid=46975"
Facts about "Xeon D-1531 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ size9 MiB (9,216 KiB, 9,437,184 B, 0.00879 GiB) +