'''[[name::Turbo Boost Technology]]''' ('''TBT''') is a [[microprocessor]] [[instance of::technology]] developed by [[designer::Intel]] that attempts to enable temporary higher performance by opportunistically and automatically increasing the processor's [[clock generator|clock]] frequency. This feature automatically kicks in on TBT-enabled processors when there is sufficient headroom - subject to power rating, temperature rating, and current limits.

Turbo Boost Technology 1.0 was first introduced announced in a white paper Intel published in [[first launched::November 2008]]. It was consequently introduced in the {{intel|Nehalem}} microarchitecture. Turbo Boost 2.0 was introduced later in 2011 in the {{intel|Sandy Bridge}} microarchitecture.

This feature is only available on [[Intel]] microprocessors that support Turbo Boost and have the feature enabled and supported (e.g. most [[operating system|OSs]]). Under various workloads, especially ones that are relatively low in power demands and are lightly threaded or not threaded at all, the processor can take advantage of the headroom by increasing the [[clock generator|clock]] frequency - while staying within thermal and electrical limits. The decision to kick into turbo boost is automatic and algorithmic in nature based on a number of factors such as: estimated current consumption, estimated power consumption, core temperature, and the number of active cores.

The number of '''active cores''', which Intel defines as cores in "C0" or "C1" states ("C3" and "C6" states are 'inactive'), dictates the upper limit. Generally, the more active cores, the lower the highest clock frequency Turbo Boost can allow as it's easier to exceed various electrical limits. For example, a [[dual-core]] 2 GHz MPU may allow a boost of 266.66 MHz (to 2266.66 MHz) when a single core is active but only 133.33 MHz (to 2133.33 MHz) when two cores are active. (Note that if the thermal and electrical limits have been exceeded, Turbo Boost will be limited even further). The notion of active cores is important because disabling [[advanced configuration and power interface|ACPI]] (e.g. C3) in an attempt to beef up performance also has the counter-consequence of potentially reducing single-core performance (as that prevents Turbo Boost from reaching maximum allowable frequency).

The upper frequency limit depends on the active core count and the [[microarchitecture]]'s {{x86|BCLK}}. The turbo frequency per each number of active cores is some multiple (called a bin upside) of the base clock, which is listed below. The exact multiplier is model-dependent.

! µarch !! {{x86|BCLK}} ||   || µarch !! {{x86|BCLK}}

| {{intel|Nehalem|l=arch}} || 133.<span style="text-decoration:overline">33</span> MHz || || {{intel|Cascade Lake|l=arch}} || 100.00 MHz

| {{intel|Westmere|l=arch}} || 133.<span style="text-decoration:overline">33</span> MHz || || {{intel|Cannon Lake|l=arch}} || 100.00 MHz

| {{intel|Sandy Bridge|l=arch}} || 100.00 MHz || || {{intel|Ice Lake|l=arch}} || 100.00 MHz

| {{intel|Ivy Bridge|l=arch}} || 100.00 MHz

| {{intel|Haswell|l=arch}} || 100.00 MHz

| {{intel|Broadwell|l=arch}} || 100.00 MHz

| {{intel|Skylake|l=arch}} || 100.00 MHz

| {{intel|Coffee Lake|l=arch}} || 100.00 MHz

[[Category:power management mechanisms by intel]]