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[[File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]]]
 
[[File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]]]
 
[[File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
 
[[File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
[[File:intel scaling roadmap to 5nm.png|250px|thumb|Intel roadmap from [[10 nm]] to [[5 nm]] and an advance packaging roadmap.]]
 
 
<div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
 
<div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
 
<table class="wikitable" style="text-align: center;">
 
<table class="wikitable" style="text-align: center;">
 
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
 
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
{{intel proc tech |year=1972 |name=PMOS I |mlayers=1 |node=10 µm
 
  |archs=4004
 
  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
 
  |a2=L<sub>g</sub>  |d2=10.0 µm
 
}}
 
{{intel proc tech |year=1974 |name=HMOS I |mlayers=1 |node=8 µm
 
  |archs=
 
  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
 
  |a2=L<sub>g</sub>  |d2=8.0 µm
 
}}
 
{{intel proc tech |year=1976 |name=HMOS II/III |mlayers=1 |node=6 µm
 
  |archs=8080
 
  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
 
  |a2=L<sub>g</sub>  |d2=6.0 µm
 
}}
 
 
{{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
 
{{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
 
   |archs=8085, 8086, 8088, 80186
 
   |archs=8085, 8086, 8088, 80186
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   |a4=CPP            |d4=336 nm    |a42=MMP            |d42=345 nm
 
   |a4=CPP            |d4=336 nm    |a42=MMP            |d42=345 nm
 
}}
 
}}
{{intel proc tech |year=2003 |name=P1262 (CPU)<br>P1263 (SoC, I/O) |mlayers=7 |node=90 nm
+
{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
 
   |xtor img=intel 90nm gate.png
 
   |xtor img=intel 90nm gate.png
 
   |interconnects img=intel_90nm_gate_interconnect.png
 
   |interconnects img=intel_90nm_gate_interconnect.png
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   |a4=CPP            |d4=260 nm    |a42=MMP            |d42=220 nm
 
   |a4=CPP            |d4=260 nm    |a42=MMP            |d42=220 nm
 
}}
 
}}
{{intel proc tech |year=2005 |name=P1264 (CPU)<br>P1265 (SoC, I/O) |mlayers=8 |node=65 nm
+
{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
 
   |xtor img=intel 65nm gate.png
 
   |xtor img=intel 65nm gate.png
 
   |interconnects img=intel_65nm_gate_interconnect.png
 
   |interconnects img=intel_65nm_gate_interconnect.png
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   |a4=CPP            |d4=220 nm    |a42=MMP            |d42=210 nm
 
   |a4=CPP            |d4=220 nm    |a42=MMP            |d42=210 nm
 
}}
 
}}
{{intel proc tech |year=2007 |name=P1266 (CPU)<br>P1267 (SoC, I/O) |mlayers=9 |node=45 nm
+
{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
 
   |xtor img=intel 45nm gate.png
 
   |xtor img=intel 45nm gate.png
 
   |interconnects img=intel_45nm_gate_interconnects.png
 
   |interconnects img=intel_45nm_gate_interconnects.png
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   |a4=CPP            |d4=160 nm    |a42=MMP            |d42=180 nm
 
   |a4=CPP            |d4=160 nm    |a42=MMP            |d42=180 nm
 
}}
 
}}
{{intel proc tech |year=2009 |name=P1268 (CPU)<br>P1269 (SoC, I/O) |mlayers=10 |node=32 nm
+
{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
 
   |xtor img=intel 32nm gate.png
 
   |xtor img=intel 32nm gate.png
 
   |interconnects img=intel 32nm gate interconnect.png
 
   |interconnects img=intel 32nm gate interconnect.png
 
   |archs=Westmere, Sandy Bridge
 
   |archs=Westmere, Sandy Bridge
   |a1=T<sub>oxe</sub>|d1=1 nm      |a12=Gate Dielectric |d12=High-κ
+
   |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
 
   |a2=V<sub>dd</sub> |d2=0.75 V    |a22=SRAM            |d22=0.148 µm²
 
   |a2=V<sub>dd</sub> |d2=0.75 V    |a22=SRAM            |d22=0.148 µm²
 
   |a3=L<sub>g</sub>  |d3=30 nm
 
   |a3=L<sub>g</sub>  |d3=30 nm
 
   |a4=CPP            |d4=112.5 nm  |a42=MMP            |d42=112.5 nm
 
   |a4=CPP            |d4=112.5 nm  |a42=MMP            |d42=112.5 nm
 
}}
 
}}
{{intel proc tech |year=2011 |name=P1270 (CPU)<br>P1271 (SoC, I/O) |mlayers=11 |node=22 nm
+
{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
 
   |xtor img=intel 22nm gate.png
 
   |xtor img=intel 22nm gate.png
 
   |interconnects img=intel 22nm gate interconnect.png
 
   |interconnects img=intel 22nm gate interconnect.png
 
   |archs=Ivy Bridge, Haswell
 
   |archs=Ivy Bridge, Haswell
   |a1=T<sub>oxe</sub>|d1=0.9 nm    |a12=Gate Dielectric |d12=High-κ
+
   |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
 
   |a2=V<sub>dd</sub> |d2=0.75 V    |a22=SRAM            |d22=0.092 µm²
 
   |a2=V<sub>dd</sub> |d2=0.75 V    |a22=SRAM            |d22=0.092 µm²
 
   |a3=L<sub>g</sub>  |d3=26 nm
 
   |a3=L<sub>g</sub>  |d3=26 nm
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   |a6=W<sub>''fin''</sub>      |d6=8 nm      |a62=H<sub>''fin''</sub> |d62=34 nm
 
   |a6=W<sub>''fin''</sub>      |d6=8 nm      |a62=H<sub>''fin''</sub> |d62=34 nm
 
}}
 
}}
{{intel proc tech |year=2014 |name=P1272 (CPU)<br>P1273 (SoC, I/O) |mlayers=12 |node=14 nm
+
{{intel proc tech |year=2014 |name=P1272 |mlayers=12 |node=14 nm
 
   |xtor img=intel 14nm gate top.png
 
   |xtor img=intel 14nm gate top.png
 
   |interconnects img=intel 14nm gate interconnect.png
 
   |interconnects img=intel 14nm gate interconnect.png
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   |a6=W<sub>''fin''</sub>      |d6=8 nm      |a62=H<sub>''fin''</sub> |d62=42-46 nm
 
   |a6=W<sub>''fin''</sub>      |d6=8 nm      |a62=H<sub>''fin''</sub> |d62=42-46 nm
 
}}
 
}}
{{intel proc tech |year=2019 |name=P1274 (CPU)<br>P1275 (SoC, I/O) |mlayers=12-13 |node=10 nm
+
{{intel proc tech |year=2017 |name=P1274 |mlayers=12 |node=10 nm
   |archs=Cannon Lake, Icelake, Tigerlake, Sapphire Rapids
+
   |archs=Cannon Lake, Icelake, Tigerlake
 
   |a1=T<sub>oxe</sub>|d1=          |a12=Gate Dielectric |d12=High-κ
 
   |a1=T<sub>oxe</sub>|d1=          |a12=Gate Dielectric |d12=High-κ
 
   |a2=V<sub>dd</sub> |d2=0.70 V    |a22=SRAM            |d22=0.0312 µm²
 
   |a2=V<sub>dd</sub> |d2=0.70 V    |a22=SRAM            |d22=0.0312 µm²
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   |a6=W<sub>''fin''</sub>      |d6=7 nm      |a62=H<sub>''fin''</sub> |d62=44-55 nm
 
   |a6=W<sub>''fin''</sub>      |d6=7 nm      |a62=H<sub>''fin''</sub> |d62=44-55 nm
 
}}
 
}}
{{intel proc tech |year=2021 |name=P1276 (CPU)<br>P1277 (SoC, I/O) |mlayers= |node=7 nm
+
{{intel proc tech |year=202? |name=P1276 |mlayers= |node=7 nm
  |archs=Granite Rapids
 
 
}}
 
}}
{{intel proc tech |year=2024 |name=P1278 (CPU)<br>P1279 (SoC, I/O) |mlayers= |node=5 nm
+
{{intel proc tech |year=202? |name=P1278 |mlayers= |node=5 nm
 
}}
 
}}
 
</table>
 
</table>

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