Editing intel/process

{{intel title|Process Technology}}
This article details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history for research and posterity.

The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers. Finally, from the [[45 nm]] node, Intel has switched to utilizing a [[high-κ]] material, therefore the oxide thickness shown refers to the [[equivalent oxide thickness]] instead.

== Timeline ==
[[File:intel 1micron yield.png|right|250px|thumb|[[1 µm]] vs [[500 nm]] yield]]
[[File:intel historical 2yr process.png|250px|thumb|historical roadmap]]
[[File:intel tech ramps 1um to 65nm.png|right|250px|thumb|Ramps from [[1 µm]] to [[65 nm]]]]
[[File:intel roadmap past 180nm.png|right|250px|thumb|Roadmap past [[180 nm]]]]
[[File:intel sram tests 130nm to 45nm.png|right|250px|thumb|SRAM test chips from [[130 nm]] to [[45 nm]]]]
[[File:intel fab roadmap from 2003.png|250px|thumb|Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.]]
[[File:intel sram density scaling.png|250px|thumb|[[65 nm]] to [[32 nm]] SRAM scaling]]
[[File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]]]
[[File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
<div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
<table class="wikitable" style="text-align: center;">
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
{{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
  |archs=8085, 8086, 8088, 80186
  |a1=T<sub>ox</sub> |d1=70 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22= 1120 µm²
  |a3=L<sub>g</sub>  |d3=3.0 µm
  |a4=CPP            |d4=7 µm      |a42=MMP             |d42=11 µm
}}
{{intel proc tech |year=1979 |name=CHMOS II |mlayers=1 |node=2 µm
  |archs=
  |a1=T<sub>ox</sub> |d1=40 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=1740 µm²
  |a3=L<sub>g</sub>  |d3=2.0 µm
  |a4=CPP            |d4=5.6 µm    |a42=MMP             |d42=8 µm
}}
{{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm
  |archs=80286, 80386
  |a1=T<sub>ox</sub> |d1=25 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=951.7 µm²
  |a3=L<sub>g</sub>  |d3=1.5 µm
  |a4=CPP            |d4=4.0 µm    |a42=MMP             |d42=6.4 µm
}}
{{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm
  |archs=80486
  |a1=T<sub>ox</sub> |d1=          |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=5 V       |a22=SRAM            |d22=220 µm²
  |a3=L<sub>g</sub>  |d3=1.0 µm
  |a4=CPP            |d4=          |a42=MMP             |d42=
}}
{{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm
  |archs=80486
  |a1=T<sub>ox</sub> |d1=15 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=4 V       |a22=SRAM            |d22=111 µm²
  |a3=L<sub>g</sub>  |d3=800 µm
  |a4=CPP            |d4=1.7 µm    |a42=MMP             |d42=2 µm
}}
{{intel proc tech |year=1991 |name=P652 |mlayers=4 |node=0.6 µm
  |archs=80486, P5
  |a1=T<sub>ox</sub> |d1=8 nm      |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=3.3 V     |a22=SRAM            |d22=
  |a3=L<sub>g</sub>  |d3=600 µm
  |a4=CPP            |d4=          |a42=MMP             |d42=1.4 µm
}}
{{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm
  |archs=P5
  |a1=T<sub>ox</sub> |d1=8 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=3.3 V      |a22=SRAM            |d22=44 µm²
  |a3=L<sub>g</sub>  |d3=500 nm
  |a4=CPP            |d4=           |a42=MMP             |d42=   
}}
{{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm
  |archs=P6
  |a1=T<sub>ox</sub> |d1=6 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=2.5 V      |a22=SRAM            |d22=20.5 µm²
  |a3=L<sub>g</sub>  |d3=350 nm
  |a4=CPP            |d4=920 nm     |a42=MMP             |d42=880 nm
}}

{{intel proc tech |year=1997 |name=P856 |mlayers=5 |node=0.25 µm
  |archs=P6
  |a1=T<sub>ox</sub> |d1=4.08 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=1.8 V      |a22=SRAM            |d22=10.26 µm²
  |a3=L<sub>g</sub>  |d3=200 nm
  |a4=CPP            |d4=500 nm     |a42=MMP             |d42=640 nm
}}
{{intel proc tech |year=1998 |name=P856.5 |mlayers=5 |node=0.25 µm
  |archs=P6
  |a1=T<sub>ox</sub> |d1=4.08 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=1.8 V      |a22=SRAM            |d22=9.26 µm²
  |a3=L<sub>g</sub>  |d3=200 nm
  |a4=CPP            |d4=475 nm     |a42=MMP             |d42=608 nm
}}

{{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm
  |xtor img=intel 180nm gate.png
  |archs=NetBurst
  |a1=T<sub>ox</sub> |d1=2.0 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=1.6 V      |a22=SRAM            |d22=5.59 µm²
  |a3=L<sub>g</sub>  |d3=130 nm
  |a4=CPP            |d4=480 nm     |a42=MMP             |d42=500 nm
}}
{{intel proc tech |year=2001 |name=P860 |mlayers=6 |node=0.13 µm
  |xtor img=intel 130nm gate.png
  |interconnects img=intel 130nm gate interconnect.png
  |archs=Pentium M
  |a1=T<sub>ox</sub> |d1=1.4 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=1.4 V      |a22=SRAM            |d22=2.45 µm²
  |a3=L<sub>g</sub>  |d3=70 nm
  |a4=CPP            |d4=336 nm     |a42=MMP             |d42=345 nm
}}
{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
  |xtor img=intel 90nm gate.png
  |interconnects img=intel_90nm_gate_interconnect.png
  |archs=Pentium M
  |a1=T<sub>ox</sub> |d1=1.2 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=1.2 V      |a22=SRAM            |d22=1.00 µm²
  |a3=L<sub>g</sub>  |d3=50 nm
  |a4=CPP            |d4=260 nm     |a42=MMP             |d42=220 nm
}}
{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
  |xtor img=intel 65nm gate.png
  |interconnects img=intel_65nm_gate_interconnect.png
  |archs=Core, Modified Pentium M
  |a1=T<sub>ox</sub> |d1=1.2 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
  |a2=V<sub>dd</sub> |d2=           |a22=SRAM            |d22=0.570 µm²
  |a3=L<sub>g</sub>  |d3=35 nm
  |a4=CPP            |d4=220 nm     |a42=MMP             |d42=210 nm
}}
{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
  |xtor img=intel 45nm gate.png
  |interconnects img=intel_45nm_gate_interconnects.png
  |archs=Penryn, Nehalem
  |a1=T<sub>oxe</sub>|d1=1 nm       |a12=Gate Dielectric |d12=High-κ
  |a2=V<sub>dd</sub> |d2=           |a22=SRAM            |d22=0.346 µm²
  |a3=L<sub>g</sub>  |d3=25 nm
  |a4=CPP            |d4=160 nm     |a42=MMP             |d42=180 nm
}}
{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
  |xtor img=intel 32nm gate.png
  |interconnects img=intel 32nm gate interconnect.png
  |archs=Westmere, Sandy Bridge
  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
  |a2=V<sub>dd</sub> |d2=0.75 V     |a22=SRAM            |d22=0.148 µm²
  |a3=L<sub>g</sub>  |d3=30 nm
  |a4=CPP            |d4=112.5 nm   |a42=MMP             |d42=112.5 nm
}}
{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
  |xtor img=intel 22nm gate.png
  |interconnects img=intel 22nm gate interconnect.png
  |archs=Ivy Bridge, Haswell
  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
  |a2=V<sub>dd</sub> |d2=0.75 V     |a22=SRAM            |d22=0.092 µm²
  |a3=L<sub>g</sub>  |d3=26 nm
  |a4=CPP            |d4=90 nm      |a42=MMP             |d42=80 nm
  |a5=P<sub>''fin''</sub>      |d5=60 nm
  |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=34 nm
}}
{{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm
  |xtor img=intel 14nm gate top.png
  |interconnects img=intel 14nm gate interconnect.png
  |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake
  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
  |a2=V<sub>dd</sub> |d2=0.70 V     |a22=SRAM            |d22=0.0499 µm²
  |a3=L<sub>g</sub>  |d3=20 nm
  |a4=CPP            |d4=70 nm      |a42=MMP             |d42=52 nm
  |a5=P<sub>''fin''</sub>      |d5=42 nm
  |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=42 nm
}}
{{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm
  |archs=Cannonlake, Icelake, Tigerlake
  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
  |a2=V<sub>dd</sub> |d2=0.70 V     |a22=SRAM            |d22=0.0312 µm²
  |a3=L<sub>g</sub>  |d3=18 nm ?
  |a4=CPP            |d4=54 nm      |a42=MMP             |d42=36 nm
  |a5=P<sub>''fin''</sub>      |d5=34 nm
  |a6=W<sub>''fin''</sub>      |d6=5 nm       |a62=H<sub>''fin''</sub> |d62=53 nm
}}
{{intel proc tech |year=2019 |name=P1276 |mlayers= |node=7 nm
}}
{{intel proc tech |year=2022 |name=P1278 |mlayers= |node=5 nm
}}
</table>
</div>

== SRAM Scaling ==
For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time.


[[File:intel sram bit cell scaling.png|900px]]
@@ Line 1: / Line 1: @@
-{{intel title|Process Technology History}}
+{{intel title|Process Technology}}
-This article details '''[[Intel]]'s [[semiconductor process technology]]''' history for research and posterity.
+This article details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history for research and posterity.
-== Overview ==
 The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. Additionally, the metal layer count is for the client dies (example consumer mobile & desktop); server models utilize considerably more layers. Finally, from the [[45 nm]] node, Intel has switched to utilizing a [[high-κ]] material, therefore the oxide thickness shown refers to the [[equivalent oxide thickness]] instead.
-== Nomenclature ==
-Intel has been using the same naming scheme for decades. All process technologies (including packaging technologies) begin with a 'P' followed by the [[wafer size]] and the process ID. Generally, the process ID is an auto-increment value with odd values generally reserved for SoC and I/O (low power) devices while the even values have been used for Intel premier line of high-performance processors.
-[[File:intel process naming scheme.svg|400px]]
 == Timeline ==
@@ Line 21: / Line 14: @@
 [[File:intel 90nm 32nm yield.png|250px|thumb|[[90 nm]] to [[32 nm]]]]
 [[File:intel scaling from 45nm to 10nm.png|250px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]]
-[[File:intel scaling roadmap to 5nm.png|250px|thumb|Intel roadmap from [[10 nm]] to [[5 nm]] and an advance packaging roadmap.]]
 <div style="overflow-x: scroll; white-space: nowrap; min-width: 300px" class="scrollable">
 <table class="wikitable" style="text-align: center;">
 <tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr>
-{{intel proc tech |year=1972 |name=PMOS I |mlayers=1 |node=10 µm
-  |archs=4004
-  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
-  |a2=L<sub>g</sub>  |d2=10.0 µm
-}}
-{{intel proc tech |year=1974 |name=HMOS I |mlayers=1 |node=8 µm
-  |archs=
-  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
-  |a2=L<sub>g</sub>  |d2=8.0 µm
-}}
-{{intel proc tech |year=1976 |name=HMOS II/III |mlayers=1 |node=6 µm
-  |archs=8080
-  |a1=Gate Dielectric |d1=SiO<sub>2</sub>
-  |a2=L<sub>g</sub>  |d2=6.0 µm
-}}
 {{intel proc tech |year=1977 |name=CHMOS I |mlayers=1 |node=3 µm
    |archs=8085, 8086, 8088, 80186
@@ Line 72: / Line 49: @@
    |a1=T<sub>ox</sub> |d1=15 nm     |a12=Gate Dielectric |d12=SiO<sub>2</sub>
    |a2=V<sub>dd</sub> |d2=4 V       |a22=SRAM            |d22=111 µm²
-   |a3=L<sub>g</sub>  |d3=800 nm
+   |a3=L<sub>g</sub>  |d3=800 µm
    |a4=CPP            |d4=1.7 µm    |a42=MMP             |d42=2 µm
 }}
@@ Line 79: / Line 56: @@
    |a1=T<sub>ox</sub> |d1=8 nm      |a12=Gate Dielectric |d12=SiO<sub>2</sub>
    |a2=V<sub>dd</sub> |d2=3.3 V     |a22=SRAM            |d22=
-   |a3=L<sub>g</sub>  |d3=600 nm
+   |a3=L<sub>g</sub>  |d3=600 µm
    |a4=CPP            |d4=          |a42=MMP             |d42=1.4 µm
 }}
@@ Line 129: / Line 106: @@
    |a4=CPP            |d4=336 nm     |a42=MMP             |d42=345 nm
 }}
-{{intel proc tech |year=2003 |name=P1262 (CPU)<br>P1263 (SoC, I/O) |mlayers=7 |node=90 nm
+{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm
    |xtor img=intel 90nm gate.png
    |interconnects img=intel_90nm_gate_interconnect.png
@@ Line 138: / Line 115: @@
    |a4=CPP            |d4=260 nm     |a42=MMP             |d42=220 nm
 }}
-{{intel proc tech |year=2005 |name=P1264 (CPU)<br>P1265 (SoC, I/O) |mlayers=8 |node=65 nm
+{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm
    |xtor img=intel 65nm gate.png
    |interconnects img=intel_65nm_gate_interconnect.png
@@ Line 147: / Line 124: @@
    |a4=CPP            |d4=220 nm     |a42=MMP             |d42=210 nm
 }}
-{{intel proc tech |year=2007 |name=P1266 (CPU)<br>P1267 (SoC, I/O) |mlayers=9 |node=45 nm
+{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm
    |xtor img=intel 45nm gate.png
    |interconnects img=intel_45nm_gate_interconnects.png
@@ Line 156: / Line 133: @@
    |a4=CPP            |d4=160 nm     |a42=MMP             |d42=180 nm
 }}
-{{intel proc tech |year=2009 |name=P1268 (CPU)<br>P1269 (SoC, I/O) |mlayers=10 |node=32 nm
+{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm
    |xtor img=intel 32nm gate.png
    |interconnects img=intel 32nm gate interconnect.png
    |archs=Westmere, Sandy Bridge
-   |a1=T<sub>oxe</sub>|d1=1 nm       |a12=Gate Dielectric |d12=High-κ
+   |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.75 V     |a22=SRAM            |d22=0.148 µm²
    |a3=L<sub>g</sub>  |d3=30 nm
    |a4=CPP            |d4=112.5 nm   |a42=MMP             |d42=112.5 nm
 }}
-{{intel proc tech |year=2011 |name=P1270 (CPU)<br>P1271 (SoC, I/O) |mlayers=11 |node=22 nm
+{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm
    |xtor img=intel 22nm gate.png
    |interconnects img=intel 22nm gate interconnect.png
    |archs=Ivy Bridge, Haswell
-   |a1=T<sub>oxe</sub>|d1=0.9 nm     |a12=Gate Dielectric |d12=High-κ
+   |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.75 V     |a22=SRAM            |d22=0.092 µm²
    |a3=L<sub>g</sub>  |d3=26 nm
@@ Line 176: / Line 153: @@
    |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=34 nm
 }}
-{{intel proc tech |year=2014 |name=P1272 (CPU)<br>P1273 (SoC, I/O) |mlayers=12 |node=14 nm
+{{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm
    |xtor img=intel 14nm gate top.png
    |interconnects img=intel 14nm gate interconnect.png
-   |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake, Cascade Lake, Comet Lake, Cooper Lake, Rocket Lake
+   |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake
    |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.70 V     |a22=SRAM            |d22=0.0499 µm²
@@ Line 185: / Line 162: @@
    |a4=CPP            |d4=70 nm      |a42=MMP             |d42=52 nm
    |a5=P<sub>''fin''</sub>      |d5=42 nm
-   |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=42-46 nm
+   |a6=W<sub>''fin''</sub>      |d6=8 nm       |a62=H<sub>''fin''</sub> |d62=42 nm
 }}
-{{intel proc tech |year=2019 |name=P1274 (CPU)<br>P1275 (SoC, I/O) |mlayers=12-13 |node=10 nm
+{{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm
-   |archs=Cannon Lake, Ice Lake, Tiger Lake, Alder Lake, Sapphire Rapids, Raptor Lake, Emerald Rapids
+   |archs=Cannonlake, Icelake, Tigerlake
    |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=High-κ
    |a2=V<sub>dd</sub> |d2=0.70 V     |a22=SRAM            |d22=0.0312 µm²
-   |a3=L<sub>g</sub>  |d3=18 nm
+   |a3=L<sub>g</sub>  |d3=18 nm ?
    |a4=CPP            |d4=54 nm      |a42=MMP             |d42=36 nm
    |a5=P<sub>''fin''</sub>      |d5=34 nm
-   |a6=W<sub>''fin''</sub>      |d6=7 nm       |a62=H<sub>''fin''</sub> |d62=44-55 nm
+   |a6=W<sub>''fin''</sub>      |d6=5 nm       |a62=H<sub>''fin''</sub> |d62=53 nm
 }}
-{{intel proc tech |year=2021 |name=P1276 (CPU)<br>P1277 (SoC, I/O) |mlayers= |node=7 nm
+{{intel proc tech |year=2019 |name=P1276 |mlayers= |node=7 nm
-  |archs=Meteor Lake, Granite Rapids
-|archs=
-  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=
-  |a2=V<sub>dd</sub> |d2=     |a22=SRAM            |d22=
-  |a3=L<sub>g</sub>  |d3=
-  |a4=CPP            |d4=     |a42=MMP          |d42=
-  |a5=P<sub>''fin''</sub>      |d5=
-  |a6=W<sub>''fin''</sub>      |d6=       |a62=H<sub>''fin''</sub> |d62=
 }}
-{{intel proc tech |year=2024 |name=P1278 (CPU)<br>P1279 (SoC, I/O) |mlayers= |node=5 nm
+{{intel proc tech |year=2022 |name=P1278 |mlayers= |node=5 nm
-|archs=
-  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=
-  |a2=V<sub>dd</sub> |d2=     |a22=SRAM            |d22=
-  |a3=L<sub>g</sub>  |d3=
-  |a4=CPP            |d4=     |a42=MMP          |d42=
-  |a5=P<sub>''fin''</sub>      |d5=
-  |a6=W<sub>''fin''</sub>      |d6=       |a62=H<sub>''fin''</sub> |d62=
-}}
-{{intel proc tech |year=2027 |name=P1280 (CPU)<br>P1281 (SoC, I/O) |mlayers= |node=3 nm
-|archs=
-  |a1=T<sub>oxe</sub>|d1=           |a12=Gate Dielectric |d12=
-  |a2=V<sub>dd</sub> |d2=     |a22=SRAM            |d22=
-  |a3=L<sub>g</sub>  |d3=
-  |a4=CPP            |d4=     |a42=MMP          |d42=
-  |a5=P<sub>''fin''</sub>      |d5=
-  |a6=W<sub>''fin''</sub>      |d6=       |a62=H<sub>''fin''</sub> |d62=
 }}
 </table>
@@ Line 228: / Line 181: @@
 == SRAM Scaling ==
-For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time. Nonetheless, the size of the SRAM can be as much as three to four times the density of the typical logic cell.
+For Intel, from [[2 µm]] to [[10 nm]], SRAM 6T [[bit cells]] have had an average shrink of 0.496x in an attempt to maintain [[Moore's Law]] double density observation/requirement. Note that SRAM shrunk more significantly prior to the [[65 nm process]] node. It should also be noted that logic typically scales better than the typical 6T SRAM cells, so raw logic density scaled more over time.
 [[File:intel sram bit cell scaling.png|900px]]
-== Other processes ==
-{{other processes list}}
-== See also ==
-* {{intel|Copy Exactly!}}
-[[Category:intel]]