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− | {{intel title|Process Technology | + | {{intel title|Process Technology}} |
− | This article details '''[[Intel]]'s [[ | + | This article details details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values; however some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used. |
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− | The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values | ||
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== Timeline == | == Timeline == | ||
− | [[File:intel 1micron yield.png|right| | + | [[File:intel 1micron yield.png|right|300px|thumb|[[1 µm]] vs [[500 nm]] yield]] |
− | + | [[File:intel tech ramps 1um to 65nm.png|right|300px|thumb|Ramps from [[1 µm]] to [[65 nm]]]] | |
− | [[File:intel tech ramps 1um to 65nm.png|right| | + | [[File:intel sram tests 130nm to 45nm.png|right|300px|thumb|SRAM test chips from [[130 nm]] to [[45 nm]]]] |
− | + | [[File:intel fab roadmap from 2003.png|300px|thumb|Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.]] | |
− | [[File:intel sram tests 130nm to 45nm.png|right| | + | [[File:intel sram density scaling.png|300px|thumb|[[65 nm]] to [[32 nm]] SRAM scaling]] |
− | [[File:intel fab roadmap from 2003.png| | + | [[File:intel 90nm 32nm yield.png|300px|thumb|[[90 nm]] to [[32 nm]]]] |
− | [[File:intel sram density scaling.png| | + | [[File:intel scaling from 45nm to 10nm.png|300px|thumb|Intel scaling from [[45 nm]] to [[10 nm]]]] |
− | [[File:intel 90nm 32nm yield.png| | + | <div style="overflow-x: scroll; white-space: nowrap;"> |
− | [[File:intel scaling from 45nm to 10nm.png| | ||
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− | <div style="overflow-x: scroll; white-space: nowrap; | ||
<table class="wikitable" style="text-align: center;"> | <table class="wikitable" style="text-align: center;"> | ||
− | <tr><th>Year</th><th>Process</th><th> | + | <tr><th>Year</th><th>Process</th><th>Node</th><th>MLayers</th><th>µarchs</th><th>Gate</th><th>Interconnects</th><th colspan="4">Attributes</th></tr> |
− | {{intel proc tech |year= | + | {{intel proc tech |year= |name=CHMOS I |mlayers=1 |node=3 µm |
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|archs=8085, 8086, 8088, 80186 | |archs=8085, 8086, 8088, 80186 | ||
− | |a1=T<sub>ox</sub> |d1=70 nm |a12=Gate Dielectric |d12= | + | |a1=T<sub>ox</sub> |d1=70 nm |a12=Gate Dielectric |d12= |
|a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22= 1120 µm² | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22= 1120 µm² | ||
|a3=L<sub>g</sub> |d3=3.0 µm | |a3=L<sub>g</sub> |d3=3.0 µm | ||
|a4=CPP |d4=7 µm |a42=MMP |d42=11 µm | |a4=CPP |d4=7 µm |a42=MMP |d42=11 µm | ||
}} | }} | ||
− | {{intel proc tech |year= | + | {{intel proc tech |year= |name=CHMOS II |mlayers=1 |node=2 µm |
|archs= | |archs= | ||
− | |a1=T<sub>ox</sub> |d1=40 nm |a12=Gate Dielectric |d12= | + | |a1=T<sub>ox</sub> |d1=40 nm |a12=Gate Dielectric |d12= |
|a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22=1740 µm² | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22=1740 µm² | ||
|a3=L<sub>g</sub> |d3=2.0 µm | |a3=L<sub>g</sub> |d3=2.0 µm | ||
Line 56: | Line 29: | ||
{{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm | {{intel proc tech |year=1982 |name=P646<br>(CHMOS III) |mlayers=1 |node=1.5 µm | ||
|archs=80286, 80386 | |archs=80286, 80386 | ||
− | |a1=T<sub>ox</sub> |d1=25 nm |a12=Gate Dielectric |d12= | + | |a1=T<sub>ox</sub> |d1=25 nm |a12=Gate Dielectric |d12=Si<sub>2</sub>N<sub>2</sub>O |
|a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22=951.7 µm² | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22=951.7 µm² | ||
|a3=L<sub>g</sub> |d3=1.5 µm | |a3=L<sub>g</sub> |d3=1.5 µm | ||
Line 63: | Line 36: | ||
{{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm | {{intel proc tech |year=1987 |name=P648 |mlayers=2 |node=1.0 µm | ||
|archs=80486 | |archs=80486 | ||
− | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12= |
− | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22= | + | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22= |
− | |a3=L<sub>g</sub> |d3=1 | + | |a3=L<sub>g</sub> |d3=1,000 µm |
− | |a4=CPP |d4= | + | |a4=CPP |d4= |a42=MMP |d42= |
}} | }} | ||
{{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm | {{intel proc tech |year=1989 |name=P650 |mlayers=3 |node=0.8 µm | ||
|archs=80486 | |archs=80486 | ||
− | |a1=T<sub>ox</sub> |d1=15 nm |a12=Gate Dielectric |d12= | + | |a1=T<sub>ox</sub> |d1=15 nm |a12=Gate Dielectric |d12= |
− | |a2=V<sub>dd</sub> |d2= | + | |a2=V<sub>dd</sub> |d2=5 V |a22=SRAM |d22=111 µm² |
− | |a3=L<sub>g</sub> |d3=800 | + | |a3=L<sub>g</sub> |d3=800 µm |
|a4=CPP |d4=1.7 µm |a42=MMP |d42=2 µm | |a4=CPP |d4=1.7 µm |a42=MMP |d42=2 µm | ||
}} | }} | ||
− | {{intel proc tech |year=1991 |name= | + | {{intel proc tech |year=1991 |name= |mlayers=4 |node=0.6 µm |
|archs=80486, P5 | |archs=80486, P5 | ||
− | |a1=T<sub>ox</sub> |d1=8 nm |a12=Gate Dielectric |d12= | + | |a1=T<sub>ox</sub> |d1=8 nm |a12=Gate Dielectric |d12= |
|a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= | |a2=V<sub>dd</sub> |d2=3.3 V |a22=SRAM |d22= | ||
− | |a3=L<sub>g</sub> |d3=600 | + | |a3=L<sub>g</sub> |d3=600 µm |
|a4=CPP |d4= |a42=MMP |d42=1.4 µm | |a4=CPP |d4= |a42=MMP |d42=1.4 µm | ||
}} | }} | ||
{{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm | {{intel proc tech |year=1993 |name=P852 |mlayers=4 |node=0.5 µm | ||
|archs=P5 | |archs=P5 | ||
− | |a1= | + | |a1=L<sub>g</sub> |d1=500 nm |
− | |a2= | + | |a2=T<sub>ox</sub> |d2=8.0 nm |a22=Gate Dielectric |d22= |
− | |a3= | + | |a3=V<sub>dd</sub> |d3=3.3 V |
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}} | }} | ||
{{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm | {{intel proc tech |year=1995 |name=P854 |mlayers=4 |node=0.35 µm | ||
Line 113: | Line 85: | ||
{{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm | {{intel proc tech |year=1999 |name=P858 |mlayers=6 |node=0.18 µm | ||
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|archs=NetBurst | |archs=NetBurst | ||
|a1=T<sub>ox</sub> |d1=2.0 nm |a12=Gate Dielectric |d12=SiO<sub>2</sub> | |a1=T<sub>ox</sub> |d1=2.0 nm |a12=Gate Dielectric |d12=SiO<sub>2</sub> | ||
Line 129: | Line 100: | ||
|a4=CPP |d4=336 nm |a42=MMP |d42=345 nm | |a4=CPP |d4=336 nm |a42=MMP |d42=345 nm | ||
}} | }} | ||
− | {{intel proc tech |year=2003 |name=P1262 | + | {{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm |
|xtor img=intel 90nm gate.png | |xtor img=intel 90nm gate.png | ||
|interconnects img=intel_90nm_gate_interconnect.png | |interconnects img=intel_90nm_gate_interconnect.png | ||
Line 138: | Line 109: | ||
|a4=CPP |d4=260 nm |a42=MMP |d42=220 nm | |a4=CPP |d4=260 nm |a42=MMP |d42=220 nm | ||
}} | }} | ||
− | {{intel proc tech |year=2005 |name=P1264 | + | {{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm |
|xtor img=intel 65nm gate.png | |xtor img=intel 65nm gate.png | ||
|interconnects img=intel_65nm_gate_interconnect.png | |interconnects img=intel_65nm_gate_interconnect.png | ||
|archs=Core, Modified Pentium M | |archs=Core, Modified Pentium M | ||
− | |a1=T<sub>ox</sub> |d1= | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12=SiO<sub>2</sub> |
|a2=V<sub>dd</sub> |d2= |a22=SRAM |d22=0.570 µm² | |a2=V<sub>dd</sub> |d2= |a22=SRAM |d22=0.570 µm² | ||
|a3=L<sub>g</sub> |d3=35 nm | |a3=L<sub>g</sub> |d3=35 nm | ||
|a4=CPP |d4=220 nm |a42=MMP |d42=210 nm | |a4=CPP |d4=220 nm |a42=MMP |d42=210 nm | ||
}} | }} | ||
− | {{intel proc tech |year=2007 |name=P1266 | + | {{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm |
|xtor img=intel 45nm gate.png | |xtor img=intel 45nm gate.png | ||
|interconnects img=intel_45nm_gate_interconnects.png | |interconnects img=intel_45nm_gate_interconnects.png | ||
|archs=Penryn, Nehalem | |archs=Penryn, Nehalem | ||
− | |a1=T<sub> | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12=High-κ |
|a2=V<sub>dd</sub> |d2= |a22=SRAM |d22=0.346 µm² | |a2=V<sub>dd</sub> |d2= |a22=SRAM |d22=0.346 µm² | ||
|a3=L<sub>g</sub> |d3=25 nm | |a3=L<sub>g</sub> |d3=25 nm | ||
|a4=CPP |d4=160 nm |a42=MMP |d42=180 nm | |a4=CPP |d4=160 nm |a42=MMP |d42=180 nm | ||
}} | }} | ||
− | {{intel proc tech |year=2009 |name=P1268 | + | {{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm |
|xtor img=intel 32nm gate.png | |xtor img=intel 32nm gate.png | ||
|interconnects img=intel 32nm gate interconnect.png | |interconnects img=intel 32nm gate interconnect.png | ||
|archs=Westmere, Sandy Bridge | |archs=Westmere, Sandy Bridge | ||
− | |a1=T<sub> | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12=High-κ |
|a2=V<sub>dd</sub> |d2=0.75 V |a22=SRAM |d22=0.148 µm² | |a2=V<sub>dd</sub> |d2=0.75 V |a22=SRAM |d22=0.148 µm² | ||
|a3=L<sub>g</sub> |d3=30 nm | |a3=L<sub>g</sub> |d3=30 nm | ||
|a4=CPP |d4=112.5 nm |a42=MMP |d42=112.5 nm | |a4=CPP |d4=112.5 nm |a42=MMP |d42=112.5 nm | ||
}} | }} | ||
− | {{intel proc tech |year=2011 |name=P1270 | + | {{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm |
|xtor img=intel 22nm gate.png | |xtor img=intel 22nm gate.png | ||
|interconnects img=intel 22nm gate interconnect.png | |interconnects img=intel 22nm gate interconnect.png | ||
|archs=Ivy Bridge, Haswell | |archs=Ivy Bridge, Haswell | ||
− | |a1=T<sub> | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12=High-κ |
|a2=V<sub>dd</sub> |d2=0.75 V |a22=SRAM |d22=0.092 µm² | |a2=V<sub>dd</sub> |d2=0.75 V |a22=SRAM |d22=0.092 µm² | ||
|a3=L<sub>g</sub> |d3=26 nm | |a3=L<sub>g</sub> |d3=26 nm | ||
|a4=CPP |d4=90 nm |a42=MMP |d42=80 nm | |a4=CPP |d4=90 nm |a42=MMP |d42=80 nm | ||
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}} | }} | ||
− | {{intel proc tech |year=2014 |name=P1272 | + | {{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm |
|xtor img=intel 14nm gate top.png | |xtor img=intel 14nm gate top.png | ||
|interconnects img=intel 14nm gate interconnect.png | |interconnects img=intel 14nm gate interconnect.png | ||
− | |archs=Broadwell, Skylake, Kaby Lake, Coffee | + | |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake |
− | |a1=T<sub> | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12=High-κ |
− | |a2=V<sub>dd</sub> |d2= | + | |a2=V<sub>dd</sub> |d2= |a22=SRAM |d22=0.0499 µm² |
|a3=L<sub>g</sub> |d3=20 nm | |a3=L<sub>g</sub> |d3=20 nm | ||
|a4=CPP |d4=70 nm |a42=MMP |d42=52 nm | |a4=CPP |d4=70 nm |a42=MMP |d42=52 nm | ||
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}} | }} | ||
− | {{intel proc tech |year= | + | {{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm |
− | |archs= | + | |archs=Cannonlake, Icelake, Tigerlake |
− | |a1=T<sub> | + | |a1=T<sub>ox</sub> |d1= |a12=Gate Dielectric |d12=High-κ |
− | |a2=V<sub>dd</sub> |d2= | + | |a2=V<sub>dd</sub> |d2= |a22=SRAM |d22=0.0312 µm² |
− | |a3=L<sub>g</sub> |d3=18 nm | + | |a3=L<sub>g</sub> |d3=18 nm ? |
|a4=CPP |d4=54 nm |a42=MMP |d42=36 nm | |a4=CPP |d4=54 nm |a42=MMP |d42=36 nm | ||
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}} | }} | ||
− | {{intel proc tech |year= | + | {{intel proc tech |year=2019 |name=P1276 |mlayers= |node=7 nm |
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}} | }} | ||
− | {{intel proc tech |year= | + | {{intel proc tech |year=2022 |name=P1278 |mlayers= |node=5 nm |
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}} | }} | ||
</table> | </table> | ||
</div> | </div> | ||
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