{{intel title|Process Technology}}

This article details details '''[[Intel]]'s [[Semiconductor Process Technology]]''' history. The table below shows the history of Intel's process scaling. Values were taken from various Intel documents including IDF presentations, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between Intel's own documents and therefore discrepancies may exist. [[SRAM]] bitcell areas refer to a high-density 6T bitcell with the exception of the very first few processes where smaller cell designs were used.

[[File:intel 1micron yield.png|right|300px|thumb|[[1 µm]] vs [[500 nm]] yield]]

[[File:intel tech ramps 1um to 65nm.png|right|300px|thumb|Ramps from [[1 µm]] to [[65 nm]]]]

[[File:intel sram tests 130nm to 45nm.png|right|300px|thumb|SRAM test chips from [[130 nm]] to [[45 nm]]]]

[[File:intel fab roadmap from 2003.png|300px|thumb|Intel's fab roadmap from 2003. Intel had to switch to FinFET after gate length scaling stalled due to subpar electrical characteristics.]]

[[File:intel sram density scaling.png|300px|thumb|[[65 nm]] to [[32 nm]] SRAM scaling]]

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<tr><th>Year</th><th>Process</th><th>Node</th><th>MLayers</th><th>µarchs</th><th>Transistor</th><th colspan="4">Attributes</th></tr>

{{intel proc tech |year= |name=CHMOS I |mlayers=1 |node=3 µm

   |a1=T_ox |d1=70 nm    |a12=Gate Dielectric |d12=

{{intel proc tech |year= |name=CHMOS II |mlayers=1 |node=2 µm

   |a1=T_ox |d1=40 nm    |a12=Gate Dielectric |d12=

   |a1=T_ox |d1=25 nm    |a12=Gate Dielectric |d12=Si₂N₂O

   |a1=L_g |d1=1,000 nm

   |a2=T_ox |d2=? nm |a22=Gate Dielectric |d22=

   |a3=V_dd |d3=? V

   |a1=L_g  |d1=800 nm

   |a2=T_ox |d2=? nm |a22=Gate Dielectric |d22=

   |a3=V_dd |d3=? V

   |a1=L_g |d1=500 nm

   |a2=T_ox |d2=8.0 nm |a22=Gate Dielectric |d22=

   |a3=V_dd |d3=3.3 V

   |a1=L_g  |d1=350 nm

   |a2=T_ox |d2=5.2 nm |a22=Gate Dielectric |d22=

   |a3=V_dd |d3=2.5 V

{{intel proc tech |year=1997 |name=P856<br>P856.5 |mlayers=5 |node=0.25 µm

   |a1=L_g |d1=200 nm

   |a2=T_ox |d2=3.1 nm |a22=Gate Dielectric |d22=SiO₂

   |a3=V_dd |d3=1.8 V

{{intel proc tech |year=2003 |name=P1262 |mlayers=7 |node=90 nm

{{intel proc tech |year=2005 |name=P1264 |mlayers=8 |node=65 nm

   |a1=T_ox |d1=           |a12=Gate Dielectric |d12=SiO₂

{{intel proc tech |year=2007 |name=P1266 |mlayers=9 |node=45 nm

   |a1=T_ox |d1=           |a12=Gate Dielectric |d12=High-κ

{{intel proc tech |year=2009 |name=P1268 |mlayers=10 |node=32 nm

   |a1=T_ox |d1=           |a12=Gate Dielectric |d12=High-κ

   |a2=V_dd |d2=           |a22=SRAM            |d22=0.148 µm²

{{intel proc tech |year=2011 |name=P1270 |mlayers=11 |node=22 nm

   |a1=T_ox |d1=           |a12=Gate Dielectric |d12=High-κ

   |a2=V_dd |d2=           |a22=SRAM            |d22=0.092 µm²

{{intel proc tech |year=2014 |name=P1272 |mlayers=11 |node=14 nm

   |archs=Broadwell, Skylake, Kaby Lake, Coffee Lake

   |a1=T_ox |d1=          |a12=Gate Dielectric |d12=High-κ

   |a2=V_dd |d2=           |a22=SRAM            |d22=0.0499 µm²

{{intel proc tech |year=2017 |name=P1274 |mlayers= |node=10 nm

   |archs=Cannonlake, Icelake, Tigerlake

   |a1=T_ox |d1=          |a12=Gate Dielectric |d12=High-κ

   |a2=V_dd |d2=           |a22=SRAM            |d22=0.0312 µm²

   |a3=L_g  |d3=18 nm ?

{{intel proc tech |year=2019 |name=P1276 |mlayers= |node=7 nm

{{intel proc tech |year=2022 |name=P1278 |mlayers= |node=5 nm