From WikiChip
Editing intel/microarchitectures/whiskey lake

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 5: Line 5:
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
−
|introduction=Q4, 2018
+
|introduction=July, 2018
−
|process=14 nm++
+
|process=14 nm
 
|cores=4
 
|cores=4
 
|oooe=Yes
 
|oooe=Yes
Line 58: Line 58:
 
|l3 desc=Up to 16-way set associative
 
|l3 desc=Up to 16-way set associative
 
|core name=Whiskey Lake U
 
|core name=Whiskey Lake U
−
|predecessor=Kaby Lake
+
|predecessor=Coffee Lake
−
|predecessor link=intel/microarchitectures/kaby lake
+
|predecessor link=intel/microarchitectures/coffee lake
−
|successor=Comet Lake
+
|successor=Icelake
−
|successor link=intel/microarchitectures/comet lake
+
|successor link=intel/microarchitectures/icelake
−
|contemporary=Coffee Lake
+
|contemporary=Cannon Lake
−
|contemporary link=intel/microarchitectures/coffee lake
+
|contemporary link=intel/microarchitectures/cannon lake
−
|contemporary 2=Amber Lake
 
−
|contemporary 2 link=intel/microarchitectures/amber lake
 
−
|contemporary 3=Cannon Lake
 
−
|contemporary 3 link=intel/microarchitectures/cannon lake
 
 
}}
 
}}
−
'''Whiskey Lake''' ('''WHL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Kaby Lake}} for ultra-low power mobile devices, launched concurrently with {{\\|Coffee Lake}} and {{\\|Amber Lake}}.  
+
'''Whiskey Lake''' ('''WHL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Coffee Lake}} for mobile devices. Whiskey Lake is expected to launch in the third quarter of [[2018]] and is manufactured on Intel's mature [[14 nm process]].
  
 
== Codenames ==
 
== Codenames ==
Line 89: Line 85:
  
 
== Technology ==
 
== Technology ==
−
Whiskey Lake is fabricated on 3rd generation improved [[14 nm process|14+++ process]].
+
Whiskey Lake is fabricated on 3rd generation improved [[14 nm process|14++ process]].
  
 
== Compatibility ==
 
== Compatibility ==
Line 109: Line 105:
  
 
=== CPUID ===
 
=== CPUID ===
−
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
+
{| class="wikitable tc1 tc2 tc3 tc4"
−
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
+
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
 
|-
 
|-
−
| rowspan="5" | {{intel|Whiskey Lake U|U|l=core}}
+
| rowspan="2" | {{intel|Whiskey Lake U|U|l=core}} || 0 || 0x6 || ? || ?
 
|-
 
|-
−
|| 0 || 0x6 || 0x8 || 0xE || 0xB
+
| colspan="4" | Family 6 Model ?
−
|-
 
−
| colspan="5" | Family 6 Model 142 Stepping 11
 
−
|-
 
−
|| 0 || 0x6 || 0x8 || 0xE || 0xC
 
−
|-
 
−
| colspan="5" | Family 6 Model 142 Stepping 12
 
 
|}
 
|}
−
 
−
Meltdown and L1TF are fixed in hardware starting with stepping 11. Stepping 12 adds hardware support for mitigation of Branch Target Injection (Spectre V2) and Speculative Store Bypass.
 
  
 
== Architecture ==
 
== Architecture ==
  
−
=== Key changes from {{\\|Kaby Lake}}===
+
=== Key changes from {{\\|Coffee Lake}}===
−
 
 
−
Speculative execution fixes - see https://www.intel.com/content/www/us/en/architecture-and-technology/engineering-new-protections-into-hardware.html
 
−
 
 
−
{{future information}}
 
−
<!--
 
 
* Package and pin-compatible with {{\\|Cannon Lake}} {{intel|Cannon Lake U|U|l=core}}
 
* Package and pin-compatible with {{\\|Cannon Lake}} {{intel|Cannon Lake U|U|l=core}}
−
* Die from {{intel|Coffee Lake U|l=core}} and {{intel|Cannon Point|l=chipset}} PCH
+
* Die from {{intel|Coffee Lake U|l=core}} and Cannon Lake PCH
−
-->
 
  
 
== Overview ==
 
== Overview ==
 
{{empty section}}
 
{{empty section}}
−
 
−
== All Whiskey Lake Chips ==
 
−
<!-- NOTE:
 
−
          This table is generated automatically from the data in the actual articles.
 
−
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
−
          created and tagged accordingly.
 
−
 
−
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
−
-->
 
−
{{comp table start}}
 
−
<table class="comptable sortable tc4">
 
−
{{comp table header|main|13:List of Whiskey Lake-based Processors}}
 
−
{{comp table header|main|10:Main processor|4:Integrated Graphics}}
 
−
{{comp table header 1|cols=Launched, Price, Family, %Cores, %Threads, %L3$, TDP, %Frequency, %Turbo, %Max Memory, Name, %Frequency, %Turbo}}
 
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Whiskey Lake]]
 
−
|?full page name
 
−
|?model number
 
−
|?first launched
 
−
|?release price
 
−
|?microprocessor family
 
−
|?core count
 
−
|?thread count
 
−
|?l3$ size
 
−
|?tdp
 
−
|?base frequency#GHz
 
−
|?turbo frequency (1 core)#GHz
 
−
|?max memory#GiB
 
−
|?integrated gpu
 
−
|?integrated gpu base frequency
 
−
|?integrated gpu max frequency
 
−
|format=template
 
−
|template=proc table 3
 
−
|searchlabel=
 
−
|sort=microprocessor family, model number
 
−
|order=asc,asc
 
−
|userparam=15
 
−
|mainlabel=-
 
−
|limit=100
 
−
}}
 
−
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microarchitecture::Whiskey Lake]]}}
 
−
</table>
 
−
{{comp table end}}
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

This page is a member of 1 hidden category:

Retrieved from "https://en.wikichip.org/wiki/intel/microarchitectures/whiskey_lake"
Facts about "Whiskey Lake - Microarchitectures - Intel"
RDF feed
codenameWhiskey Lake +
core count4 +
designerIntel +
first launchedApril 2018 +
full page nameintel/microarchitectures/whiskey lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameWhiskey Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +