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Latest revision Your text
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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
−
|introduction=April, 2021
+
|introduction=2020
−
|process=10 nm +
+
|process=10 nm
−
|cores=8
 
−
|cores 2=10
 
−
|cores 3=12
 
−
|cores 4=16
 
−
|cores 5=18
 
−
|cores 6=20
 
−
|cores 7=24
 
−
|cores 8=26
 
−
|cores 9=28
 
−
|cores 10=32
 
−
|cores 11=36
 
−
|cores 12=38
 
−
|cores 13=40
 
−
|oooe=Yes
 
−
|speculative=Yes
 
−
|renaming=Yes
 
−
|stages min=14
 
−
|stages max=19
 
−
|decode=5-way
 
 
|isa=x86-64
 
|isa=x86-64
−
|l1i=32 KiB
 
−
|l1i per=core
 
−
|l1i desc=8-way set associative
 
−
|l1d=48 KiB
 
−
|l1d per=core
 
−
|l1d desc=12-way set associative
 
−
|l2=1.25 MiB
 
−
|l2 per=core
 
−
|l2 desc=20-way set associative
 
−
|l3=1.5 MiB
 
−
|l3 per=core
 
−
|l3 desc=12-way set associative
 
 
|core name=Ice Lake SP
 
|core name=Ice Lake SP
 
|core name 2=Ice Lake X
 
|core name 2=Ice Lake X
−
|predecessor=Cascade Lake
+
|predecessor=Cooper Lake
−
|predecessor link=intel/microarchitectures/cascade lake
+
|predecessor link=intel/microarchitectures/cooper lake
 
|successor=Sapphire Rapids
 
|successor=Sapphire Rapids
 
|successor link=intel/microarchitectures/sapphire rapids
 
|successor link=intel/microarchitectures/sapphire rapids
−
|contemporary=Cooper Lake
+
|contemporary=Ice Lake (client)
−
|contemporary link=intel/microarchitectures/cooper lake
+
|contemporary link=intel/microarchitectures/ice_lake_(client)
−
|contemporary 2=Ice Lake (client)
 
−
|contemporary 2 link=intel/microarchitectures/ice_lake_(client)
 
 
}}
 
}}
−
'''Ice Lake''' ('''ICL''', '''ICX''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers.
+
'''Ice Lake''' ('''ICL''') '''Server Configuration''' is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[10 nm]] [[microarchitecture]] for enthusiasts and servers.
  
 
== Codenames ==
 
== Codenames ==
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| {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors
 
| {{intel|Ice Lake SP|l=core}} || ICL-SP || Server Scalable Processors
 
|}
 
|}
−
 
−
== Release Dates ==
 
−
[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|{{\\|Cooper Lake}} and Ice Lake roadmap.]]
 
−
Ice Lake server processors were said to launch in the first half of 2021.
 
  
 
== Process Technology==
 
== Process Technology==
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! Compiler !! Arch-Specific || Arch-Favorable
 
! Compiler !! Arch-Specific || Arch-Favorable
 
|-
 
|-
−
| [[ICC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
+
| [[ICC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code>
 
|-
 
|-
−
| [[GCC]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
+
| [[GCC]] || <code>-march=icelake</code> || <code>-mtune=icelake</code>
 
|-
 
|-
−
| [[LLVM]] || <code>-march=icelake-server</code> || <code>-mtune=icelake-server</code>
+
| [[LLVM]] || <code>-march=icelake</code> || <code>-mtune=icelake</code>
 
|-
 
|-
−
| [[Visual Studio]] || <code>/arch=AVX512</code> || <code>/tune:?</code>
+
| [[Visual Studio]] || <code>/?</code> || <code>/tune:?</code>
 
|}
 
|}
  
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| colspan="4" | Family 6 Model ?
 
| colspan="4" | Family 6 Model ?
 
|-
 
|-
−
| rowspan="2" | SP || 0 || 0x6 || 6 || A
+
| rowspan="2" | ? || 0 || 0x6 || ? || ?
 
|-
 
|-
−
| colspan="4" | Family 6 Model 106
+
| colspan="4" | Family 6 Model ?
 
|}
 
|}
  
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=== Key changes from {{\\|Cascade Lake}}===
 
=== Key changes from {{\\|Cascade Lake}}===
 +
{{future information}}
 +
 
* Enhanced "10nm+" (from [[14 nm]])
 
* Enhanced "10nm+" (from [[14 nm]])
−
* {{\\|Sunny Cove|Sunny Cove core}}
 
−
** ''See {{\\|Sunny Cove}} for microarchitectural details and changes''
 
 
* I/O
 
* I/O
 
** PCIe 4.0 (from PCIe 3.0)
 
** PCIe 4.0 (from PCIe 3.0)
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** Octa-channel (up from hexa-channel)  
 
** Octa-channel (up from hexa-channel)  
 
** 3200 MT/s (up from 2933 MT/s)
 
** 3200 MT/s (up from 2933 MT/s)
−
** Optane DC DIMMs
 
−
*** Apache Pass '''→''' Barlow Pass
 
 
* Platform
 
* Platform
 
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}}
 
** {{intel|Purley|l=platform}} '''→''' {{intel|Whitley|l=platform}}
 
* Packaging
 
* Packaging
−
** 4189-contact flip-chip LGA (up from 3647 contacts)
+
** 4198-contact flip-chip LGA (up from 3647 contacts)
−
{{expand list}}
 
  
 
====New instructions ====
 
====New instructions ====
−
Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details.
+
Ice Lake introduced a number of {{x86|extensions|new instructions}}:
 +
 
 +
* {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
 +
* {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID
 +
* Additional {{x86|AVX-512}} extensions:
 +
** {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} -  AVX-512 Vector Population Count Doubleword and Quadword
 +
** {{x86|AVX512VNNI|<code>AVX512VNNI</code>}} -  AVX-512 Vector Neural Network Instructions
 +
** {{x86|AVX512GFNI|<code>AVX512GFNI</code>}} -  AVX-512 Galois Field New Instructions
 +
** {{x86|AVX512VAES|<code>AVX512VAES</code>}} -  AVX-512 Vector AES
 +
** {{x86|AVX512VBMI2|<code>AVX512VBMI2</code>}} -  AVX-512 Vector Bit Manipulation, Version 2
 +
** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} -  AVX-512 Bit Algorithms
 +
** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} -  AVX-512 Vector Vector Carry-less Multiply
 +
* {{x86|TME|<code>TME</code>}} - Total Memory Encryption
 +
* {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions
 +
* Fast Short REP MOV
 +
* Split Lock Detection
  
 
== All Ice Lake Chips ==
 
== All Ice Lake Chips ==

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Facts about "Ice Lake (server) - Microarchitectures - Intel"
RDF feed
codenameIce Lake (server) +
core count8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 +
designerIntel +
first launchedApril 2021 +
full page nameintel/microarchitectures/ice lake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (server) +
pipeline stages (max)19 +
pipeline stages (min)14 +