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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|introduction=June 18, 2020
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|introduction=2019
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|process=14 nm++
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|process=14 nm
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|cores=28
 
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|cores 2=24
 
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|cores 3=20
 
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|cores 4=18
 
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|cores 5=16
 
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|cores 6=8
 
 
|type=Superscalar
 
|type=Superscalar
 
|oooe=Yes
 
|oooe=Yes
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|l1d per=core
 
|l1d per=core
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
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|l1=64 KiB
 
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|l1 per=core
 
 
|l2=1 MiB
 
|l2=1 MiB
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|l2 per=Core
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|l2 per=core
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l3=1.375 MiB
 
|l3=1.375 MiB
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|predecessor=Cascade Lake
 
|predecessor=Cascade Lake
 
|predecessor link=intel/microarchitectures/cascade lake
 
|predecessor link=intel/microarchitectures/cascade lake
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|successor=Sapphire Rapids
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|successor=Ice Lake (Server)
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|successor link=intel/microarchitectures/sapphire rapids
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|successor link=intel/microarchitectures/ice lake (server)
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|contemporary=Ice Lake (Server)
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|contemporary=Coffee Lake
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|contemporary link=intel/microarchitectures/ice lake (server)
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|contemporary link=intel/microarchitectures/coffee lake
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|contemporary 2=Coffee Lake
 
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|contemporary 2 link=intel/microarchitectures/coffee lake
 
 
}}
 
}}
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'''Cooper Lake''' ('''CPL''' / '''CPX''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for the multiprocessing server market only.
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'''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers.
  
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Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while {{\\|Ice Lake (Server)|Ice Lake}} serves the single and dual-socket segments.
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For desktop enthusiasts, Cascade Lake is branded {{intel|Core i7}}, and {{intel|Core i9}} processors (under the {{intel|Core X}} series). For scalable server class processors, Intel branded it as {{intel|Xeon Bronze}}, {{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}}.
  
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For scalable server class processors, Intel branded it as {{intel|Xeon Gold}} and {{intel|Xeon Platinum}}.
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 +
{{future information}}
  
 
== Codenames ==
 
== Codenames ==
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Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
 
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
 
! Core !! Abbrev !! Target
 
! Core !! Abbrev !! Target
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|- style="text-decoration:line-through"
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|-
 
| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
 
| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market
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|- style="text-decoration:line-through"
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|-
 
| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
 
| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations
 
|-
 
|-
 
| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
 
| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors
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|- style="text-decoration:line-through"
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|-
 
| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
 
| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors
 
|}
 
|}
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== Release Dates ==
 
== Release Dates ==
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[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]]
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Cooper Lake is expected to be released in mid-2019.
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Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
 
  
 
== Process Technology ==
 
== Process Technology ==
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Cooper Lake is fabricated on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]].
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Cascade Lake is fabricated on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]].
  
 
== Architecture ==
 
== Architecture ==
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As with {{\\|Cascade Lake}}, Cooper Lake is also based on the {{intel|Purley|l=platform}} platform and is designed as a drop-in upgrade.
 
=== Key changes from {{\\|Cascade Lake}} ===
 
=== Key changes from {{\\|Cascade Lake}} ===
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* SoC
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{{empty section}}
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** 2x UPI links (6, up from 3)
 
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* Memory
 
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** Higher data rate (3200 MT/s, up from 2933 MT/s)
 
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** Optane DC DIMMs
 
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*** Apache Pass '''→''' Barlow Pass
 
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* Platform
 
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** {{intel|Purley|l=platform}} '''→''' {{intel|Cedar Island|l=platform}}
 
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* Packaging
 
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** Socket-P+
 
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*** 4189-contact flip-chip LGA (up from 3647 contacts)
 
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{{expand list}}
 
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====New instructions ====
 
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Cooper Lake introduced a number of {{x86|extensions|new instructions}}:
 
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* [[BFLOAT16]] - A new data type for [[acceleration]] of [[neural processor|AI workloads]].
 
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* {{x86|AVX512 BF16}} - AVX-512 [[Brain Float 16]] extension
 
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== See also ==
 
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* {{\\|Ice Lake (Server)}}
 

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Facts about "Cooper Lake - Microarchitectures - Intel"
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codenameCooper Lake +
core count28 +, 24 +, 20 +, 18 +, 16 + and 8 +
designerIntel +
first launchedJune 18, 2020 +
full page nameintel/microarchitectures/cooper lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCooper Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +