Editing intel/microarchitectures/alder lake

{{intel title|Alder Lake|arch}}
{{microarchitecture
|atype=CPU
|name=Alder Lake
|designer=Intel
|manufacturer=Intel
|introduction=2021
|process=intel 7 (10nm ESF)
|cores=8P+8E
|cores 2=6P+8E
|cores 3=6P+0E
|cores 4=2P+8E
|processing elements=32 EU igpu
|processing elements 2=96 EU igpu
|oooe=Yes
|speculative=Yes
|renaming=Yes
|isa=x86-64
|extension=MMX
|extension 2=AVX
|extension 3=AVX2
|extension 4=AVX-512 (needs BIOS support and no E core)
|l1i=32 KB
|l1i per=core
|l1d=48 KB (P) / 64 KB (E)
|l1d per=core
|l1=80 KB (P) / 96 KB (E)
|l1 per=core
|l2=1.25 MB (P) / 2MB (4E)
|l2 per=core
|l3=up to 30 MB
|core name=[[::intel/microarchitectures/golden_cove|Golden Cove]]
|core name 2=[[::intel/microarchitectures/gracemont|Gracemont]]
|predecessor=Tiger Lake
|predecessor link=intel/microarchitectures/tiger lake
|predecessor 2=Rocket Lake
|predecessor 2 link=intel/microarchitectures/rocket lake
|predecessor 3=Lakefield
|predecessor 3 link=intel/microarchitectures/lakefield
|successor=Raptor Lake
|successor link=intel/microarchitectures/raptor lake
|successor 2=Meteor Lake
|successor 2 link=intel/microarchitectures/meteor lake
}}
'''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to both {{\\|Tiger Lake}} and {{\\|Rocket Lake}}, an [[Intel 7]]-process based [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. Alder Lake is Intel's first [[10-nanometer]]-class proper successor to all prior generation of processors - spanning from ultra-low power to desktop and workstations. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]].

For desktop and mobile, Alder Lake is branded as 12th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}}, and {{intel|Core i9}} processors.

== Codenames ==
{| class="wikitable"
|-
! Core !! Abbrev !! Platform !! Target
|-
| {{intel|Alder Lake M|l=core}} || ADL-M || || Light notebooks, 2-in-1s detachable, tablets, conference room, computer sticks, etc.
|-
| {{intel|Alder Lake P|l=core}} || ADL-P || || Ultimate mobile performance, mobile workstations, portable All-in-Ones (AiOs), Minis
|-
| {{intel|Alder Lake S|l=core}} || ADL-S || || Desktop performance to value, AiOs, and minis
|}

== Brands ==
Intel released Alder Lake under 3 main brand families for mainstream workstations, desktops, and mobile.

{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! {{intel|Turbo Boost Max|TBMT}}
|-
| [[File:core i5 logo (2020).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || style="text-align: left;" | Mid-range Performance || [[10 cores|10]] (6+4) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
|-
| [[File:core i7 logo (2020).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | High-end Performance || [[12 cores|12]] (8+4) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}}
|-
| [[File:core i9 logo (2020).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || style="text-align: left;" | Extreme Performance || [[16 cores|16]] (8+8) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}}
|}

== Process Technology==
Intel is planning Alder Lake to be built on an improved Intel 7 node (previously 10nm Enhanced SuperFin (ESF)). This will be the case for both the powerful Golden Cove cores, and Gracemont cores.

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=alderlake</code> || <code>-mtune=alderlake</code>
|-
| [[GCC]] || <code>-march=alderlake</code> || <code>-mtune=alderlake</code>
|-
| [[LLVM]] || <code>-march=alderlake</code> || <code>-mtune=alderlake</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:alderlake</code>
|}

=== CPUID ===
{| class="wikitable tc1 tc2 tc3 tc4"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
|-
| rowspan="2" | {{intel|Alder Lake P|P|l=core}} || 0 || 0x6 || 0x9 || 0x7
|-
| colspan="4" | Family 6 Model 151
|-
| rowspan="2" | {{intel|Alder Lake S|S|l=core}} || 0 || 0x6 || 0x9 || 0xA
|-
| colspan="4" | Family 6 Model 154
|}

== History ==
In January 2021 Intel teased Alder Lake in their CES 2021 speech. On the July 26th's Intel Accelerated webcast, CEO Pat Gelsinger hinted at the Alder Lake lineup being released at a future event called "Intel Innovation" which aired between October 27-28th.

== Architecture ==

=== Key changes from {{\\|Tiger Lake}}===
* Core
** Hybrid Golden Cove (big core) & Gracemont (small core) microarchitecture
** Higher IPC(Intel self-reported 19% IPC)
*** Some common integer ALU ops (CMP,TEST,AND,OR,XOR,LEA) increased throughput by 1 insn/cycle
*** Vector floating point addition/subtraction latency decreased from 4 to 2 cycles
*** [V]PCLMULQDQ latency decreased from 8/6 to 3 cycles
** Intel 7 node
* Memory
** Support for DDR5
** Speeds of at least 4800MHz, up to 5600MHz
* Improved power delivery system

== Overview == 
Alder Lake departs from all prior Intel SoCs by featuring the company's first mainstream implementation of a single-ISA heterogeneous multi-core microarchitecture. While not the first ({{\\|Lakefield}} was), Alder Lake is the first to target all market segments from mobile to desktop and workstation. The overall microarchitecture builds on its its predecessor, {{\\|Tigerlake}} but expends on its by integrating two vastly different types of cores - up to eight [[big cores]] based on the {{\\|Golden Cove}} microarchitecture and up to eight [[small cores]] based on the {{\\|Gracemont}} microarchitecture. The big cores are designed to push single-thread performance while the small cores are designed to push multi-thread power efficiency. By finely orchestrating thread scheduling based on performance demand, Alder Lake is able to provide both higher multi-threading performance-efficiency and better single-thread performance.

=== SoC design ===
{{empty section}}

== Die ==
Alder Lake comes in four die variants depending on the market segment.

{| class="wikitable"
! colspan="4" | Die
|-
! Name !! Configuration !! Dimensions !! Area
|-
| rowspan="2" | ADL-S || 8P + 8E || 10.5 mm x 20.5 mm || 215.25 mm²
|-
| 6P + 0E || 10.5 mm x 15.5 mm || 162.75 mm²
|-
| ADL-P || 6P + 8E
|-
| ADL-M || 2P + 8E
|}

=== ADL-S (8P+8E) ===
* 8 performance cores + 8 efficiency cores
* [[Intel 7]] process
* 10.5 mm x 20.5 mm
** 215.25 mm² die size


:[[File:alder lake die 2.png|900px]]


:[[File:alder lake die.png|850px]]

=== ADL-S (6P+0E) ===
* 6 performance cores, no efficiency cores
* [[Intel 7]] process
* 10.5 mm x 15.5 mm
** 162.75 mm² die size

=== Additional Shots ===
[[File:alder lake partial wafer shot.jpg|850px]]
codename	Alder Lake +
designer	Intel +
first launched	2021 +
full page name	intel/microarchitectures/alder lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Alder Lake +
processing element count	32 EU igpu + and 96 EU igpu +