From WikiChip
Editing intel/microarchitectures/alder lake
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 6: | Line 6: | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|introduction=2021 | |introduction=2021 | ||
− | |process= | + | |process=10 nm |
− | |cores= | + | |cores=8+8 |
− | |cores 2= | + | |cores 2=6+8 |
− | |cores 3= | + | |cores 3=6+0 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|isa=x86-64 | |isa=x86-64 | ||
− | + | |core name=Golden Cove | |
− | + | |core name 2=Gracemont | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |core name= | ||
− | |core name 2= | ||
|predecessor=Tiger Lake | |predecessor=Tiger Lake | ||
|predecessor link=intel/microarchitectures/tiger lake | |predecessor link=intel/microarchitectures/tiger lake | ||
|predecessor 2=Rocket Lake | |predecessor 2=Rocket Lake | ||
|predecessor 2 link=intel/microarchitectures/rocket lake | |predecessor 2 link=intel/microarchitectures/rocket lake | ||
− | |||
− | |||
|successor=Raptor Lake | |successor=Raptor Lake | ||
|successor link=intel/microarchitectures/raptor lake | |successor link=intel/microarchitectures/raptor lake | ||
− | |||
− | |||
}} | }} | ||
− | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to | + | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to {{\\|Tiger Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
− | |||
− | |||
== Codenames == | == Codenames == | ||
Line 57: | Line 32: | ||
|- | |- | ||
| {{intel|Alder Lake S|l=core}} || ADL-S || || Desktop performance to value, AiOs, and minis | | {{intel|Alder Lake S|l=core}} || ADL-S || || Desktop performance to value, AiOs, and minis | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
Line 98: | Line 55: | ||
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Alder Lake | + | | rowspan="2" | {{intel|Alder Lake P|P|l=core}} || 0 || 0x6 || 0x9 || 0x7 |
|- | |- | ||
| colspan="4" | Family 6 Model 151 | | colspan="4" | Family 6 Model 151 | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Alder Lake | + | | rowspan="2" | {{intel|Alder Lake S|S|l=core}} || 0 || 0x6 || 0x9 || 0xA |
|- | |- | ||
| colspan="4" | Family 6 Model 154 | | colspan="4" | Family 6 Model 154 | ||
Line 111: | Line 68: | ||
== Architecture == | == Architecture == | ||
+ | |||
=== Key changes from {{\\|Tiger Lake}}=== | === Key changes from {{\\|Tiger Lake}}=== | ||
* Core | * Core | ||
− | ** Hybrid Golden Cove ( | + | ** Hybrid Golden Cove (big core) & Gracemont (small core) microarchitecture |
− | ** | + | ** At least 20% IPC improvements |
− | |||
− | |||
− | |||
** Intel 7 node | ** Intel 7 node | ||
* Memory | * Memory | ||
Line 124: | Line 79: | ||
** Speeds of at least 4800MHz, up to 5600MHz | ** Speeds of at least 4800MHz, up to 5600MHz | ||
* Improved power delivery system | * Improved power delivery system | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Die == | == Die == | ||
Line 135: | Line 84: | ||
{| class="wikitable" | {| class="wikitable" | ||
− | ! colspan=" | + | ! colspan="4" | Die |
|- | |- | ||
− | ! Name !! | + | ! Name !! Configuration !! Dimensions !! Area |
|- | |- | ||
− | | rowspan="2" | ADL-S || 8P + 8E | + | | rowspan="2" | ADL-S || 8P + 8E || 10.5 mm x 20.5 mm || 215.25 mm² |
|- | |- | ||
− | | 6P + | + | | 6P + 8E || 10.5 mm x 15.5 mm || 162.75 mm² |
|- | |- | ||
− | | ADL-P || 6P + 8E | + | | ADL-P || 6P + 8E |
|- | |- | ||
| ADL-M || 2P + 8E | | ADL-M || 2P + 8E | ||
Line 150: | Line 99: | ||
=== ADL-S (8P+8E) === | === ADL-S (8P+8E) === | ||
* 8 performance cores + 8 efficiency cores | * 8 performance cores + 8 efficiency cores | ||
− | |||
* [[Intel 7]] process | * [[Intel 7]] process | ||
* 10.5 mm x 20.5 mm | * 10.5 mm x 20.5 mm | ||
Line 163: | Line 111: | ||
=== ADL-S (6P+0E) === | === ADL-S (6P+0E) === | ||
* 6 performance cores, no efficiency cores | * 6 performance cores, no efficiency cores | ||
− | |||
* [[Intel 7]] process | * [[Intel 7]] process | ||
* 10.5 mm x 15.5 mm | * 10.5 mm x 15.5 mm |
Facts about "Alder Lake - Microarchitectures - Intel"
codename | Alder Lake + |
designer | Intel + |
first launched | 2021 + |
full page name | intel/microarchitectures/alder lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Alder Lake + |
processing element count | 32 EU igpu + and 96 EU igpu + |