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|manufacturer=Intel | |manufacturer=Intel | ||
|introduction=2021 | |introduction=2021 | ||
− | |process= | + | |process=10 nm |
− | |cores= | + | |cores=8+8 |
− | |cores 2= | + | |cores 2=6+8 |
− | |cores 3= | + | |cores 3=6+0 |
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|isa=x86-64 | |isa=x86-64 | ||
− | + | |core name=Golden Cove | |
− | + | |core name 2=Gracemont | |
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− | |core name= | ||
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|predecessor=Tiger Lake | |predecessor=Tiger Lake | ||
|predecessor link=intel/microarchitectures/tiger lake | |predecessor link=intel/microarchitectures/tiger lake | ||
|predecessor 2=Rocket Lake | |predecessor 2=Rocket Lake | ||
|predecessor 2 link=intel/microarchitectures/rocket lake | |predecessor 2 link=intel/microarchitectures/rocket lake | ||
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|successor=Raptor Lake | |successor=Raptor Lake | ||
|successor link=intel/microarchitectures/raptor lake | |successor link=intel/microarchitectures/raptor lake | ||
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}} | }} | ||
− | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to | + | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to {{\\|Tiger Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
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== Codenames == | == Codenames == | ||
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| {{intel|Alder Lake S|l=core}} || ADL-S || || Desktop performance to value, AiOs, and minis | | {{intel|Alder Lake S|l=core}} || ADL-S || || Desktop performance to value, AiOs, and minis | ||
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|} | |} | ||
== Process Technology== | == Process Technology== | ||
Intel is planning Alder Lake to be built on an improved Intel 7 node (previously 10nm Enhanced SuperFin (ESF)). This will be the case for both the powerful Golden Cove cores, and Gracemont cores. | Intel is planning Alder Lake to be built on an improved Intel 7 node (previously 10nm Enhanced SuperFin (ESF)). This will be the case for both the powerful Golden Cove cores, and Gracemont cores. | ||
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== History == | == History == | ||
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== Architecture == | == Architecture == | ||
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=== Key changes from {{\\|Tiger Lake}}=== | === Key changes from {{\\|Tiger Lake}}=== | ||
* Core | * Core | ||
− | ** Hybrid Golden Cove ( | + | ** Hybrid Golden Cove (big core) & Gracemont (small core) microarchitecture |
− | ** | + | ** At least 20% IPC improvements |
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** Intel 7 node | ** Intel 7 node | ||
* Memory | * Memory | ||
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** Speeds of at least 4800MHz, up to 5600MHz | ** Speeds of at least 4800MHz, up to 5600MHz | ||
* Improved power delivery system | * Improved power delivery system | ||
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== Die == | == Die == | ||
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{| class="wikitable" | {| class="wikitable" | ||
− | ! colspan=" | + | ! colspan="4" | Die |
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− | ! Name !! | + | ! Name !! Configuration !! Dimensions !! Area |
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− | | rowspan="2" | ADL-S || 8P + 8E | + | | rowspan="2" | ADL-S || 8P + 8E || 10.5 mm x 20.5 mm || 215.25 mm² |
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− | | 6P + | + | | 6P + 8E || 10.5 mm x 15.5 mm || 162.75 mm² |
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− | | ADL-P || 6P + 8E | + | | ADL-P || 6P + 8E |
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| ADL-M || 2P + 8E | | ADL-M || 2P + 8E | ||
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=== ADL-S (8P+8E) === | === ADL-S (8P+8E) === | ||
* 8 performance cores + 8 efficiency cores | * 8 performance cores + 8 efficiency cores | ||
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* [[Intel 7]] process | * [[Intel 7]] process | ||
* 10.5 mm x 20.5 mm | * 10.5 mm x 20.5 mm | ||
** 215.25 mm² die size | ** 215.25 mm² die size | ||
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:[[File:alder lake die.png|850px]] | :[[File:alder lake die.png|850px]] | ||
=== ADL-S (6P+0E) === | === ADL-S (6P+0E) === | ||
− | * 6 performance cores | + | * 6 performance cores + 8 efficiency cores |
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* [[Intel 7]] process | * [[Intel 7]] process | ||
* 10.5 mm x 15.5 mm | * 10.5 mm x 15.5 mm |
Facts about "Alder Lake - Microarchitectures - Intel"
codename | Alder Lake + |
designer | Intel + |
first launched | 2021 + |
full page name | intel/microarchitectures/alder lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Alder Lake + |
processing element count | 32 EU igpu + and 96 EU igpu + |