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{{intel title|Crystal Well}}
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'''Crystal Well''' is the codename for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the [[Iris Pro]]-equipped [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is package together with it. Crystal Well based processors started shipping in the third quarter of 2013.
'''[[name::Crystal Well]]''' is the [[instance of::codename]] for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris Pro]]-equipped [[manufacturer::Intel]] [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.
 
  
== Details ==
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Crystal Well is a true 128MB [[L4 Cache|L4$]] which could be utilized by the core itself, not just by the [[Iris Pro]]'s Framebuffer. I.E. L3$ values that gets evicted go into the L4$. The L4$ caches bother GPU and CPU memory accesses; memory is partitioned between. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
Crystal Well is a true 128MB [[L4 Cache|L4$]] which could be utilized by the core itself, not just by the [[Iris Pro]]'s [[framebuffer]]. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
 
  
[[Intel]] has not disclosed many technical specs regarding how the Crystal Well die communicates with the main die. Intel has stated that the cache is capable of delivering 100GB/s bandwidth (50GB/s in each direction).
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[[Intel]] has not disclose much technical specs regarding how the crystal well die communicates with the main die. Intel has stated that the cache is capable of delivering 100GB/s bandwidth (50GB/s in each direction).
 
 
Note that since {{intel|Skylake|l=arch}}, Intel has changed how the [[eDRAM]] works to act as a side cache instead of an L4 cache (see {{intel|Skylake#eDRAM_architectural_changes|l=arch}} for details).
 
  
 
== Processors ==
 
== Processors ==
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! colspan="9" style="background:#D6D6FF;" | Crystal Well Processors
          created and tagged with [[has feature::Crystal Well]] property.
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! Family !! Number !! Launch Date !! Cores !! Threads !! Clock !! Lithography !! TDP !! Die Size
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4950HQ|4950HQ]]   ||Q3 2013  ||4 ||8 ||2.4 GHz  ||22 nm ||47 W || 37.5mm x 32mm
<table class="wikitable sortable">
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|-
<tr><th colspan="9" style="background:#D6D6FF;">Crystal Well Processors</th></tr>
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4850HQ|4850HQ]]  ||Q3 2013  ||4 ||8 ||2.3 GHz  ||22 nm ||47 W || 37.5mm x 32mm
<tr><th>Model</th><th>[[microprocessor family|Family]]</th><th>Microarchitecture</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Frequency</th><th>TDP</th><th>Process</th></tr>
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4750HQ|4750HQ]]  ||Q3 2013  ||4 ||8 ||2 GHz ||22 nm ||47 W || 37.5mm x 32mm
    [[Category:microprocessor models by intel]]
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|-
    [[has feature::Crystal Well]]
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4960HQ|4960HQ]]  ||Q4 2013  ||4 ||8 ||2.6 GHz  ||22 nm ||47 W || 37.5mm x 32m
  |?full page name
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|-
|?model number
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|[[Intel Core i7|Core i7]] || [[Intel Core i7-4770R|4770R]]    ||Q2 2013  ||4 ||8 ||3.2 GHz  ||22 nm ||65 W || 37.5mm x 32mm
  |?microprocessor family
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|-
|?microarchitecture
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|[[Intel Core i5|Core i5]] || [[Intel Core i5-4570R|4570R]] || Q2 2013 || 4 || 8 ||2.7 GHz ||22 nm ||65 W || 37.5mm x 32mm
  |?first launched
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|-
|?core count
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|[[Intel Core i5|Core i5]] || [[Intel Core i5-4670R|4670R]] || Q2 2013 || 4 || 8 ||3 GHz  ||22 nm ||65 W || 37.5mm x 32mm
  |?thread count
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|}
|?base frequency
 
  |?tdp
 
|?process
 
  |format=template
 
|template=proc table 1
 
|mainlabel=-
 
  |userparam=10
 
}}
 
</table>
 
 
 
== See also ==
 
* {{intel|Iris Pro Graphics 5200}}
 
  
 
== External links ==
 
== External links ==
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[[Category:intel]]
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[[Category:Intel microarchitectures]]
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[[Category:Microarchitectures]]

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