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{{intel title|Crystal Well}}
 
{{intel title|Crystal Well}}
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'''[[name::Crystal Well]]''' is the [[instance of::codename]] for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris Pro]]-equipped [[manufacturer::Intel]] [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.
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'''[[codename::Crystal Well]]''' is the codename for the L4 cache, a discrete [[eDRAM]] silicon die, which is featured in the high-end [[Iris Pro]]-equipped Intel [[Haswell]] microprocessors. The eDRAM silicon die is separate from the main [[Haswell]] die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.
  
 
== Details ==
 
== Details ==
 
Crystal Well is a true 128MB [[L4 Cache|L4$]] which could be utilized by the core itself, not just by the [[Iris Pro]]'s [[framebuffer]]. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
 
Crystal Well is a true 128MB [[L4 Cache|L4$]] which could be utilized by the core itself, not just by the [[Iris Pro]]'s [[framebuffer]]. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
  
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[[Intel]] has not disclosed many technical specs regarding how the Crystal Well die communicates with the main die. Intel has stated that the cache is capable of delivering 100GB/s bandwidth (50GB/s in each direction).
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[[Intel]] has not disclosed many technical specs regarding how the Crystal Well die communicates with the main die. Intel has stated that the cache is capable of delivering 100GB/s bandwidth (50GB/s in each direction).
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Note that since {{intel|Skylake|l=arch}}, Intel has changed how the [[eDRAM]] works to act as a side cache instead of an L4 cache (see {{intel|Skylake#eDRAM_architectural_changes|l=arch}} for details).
 
  
 
== Processors ==
 
== Processors ==
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           If a microprocessor is missing from the list, an appropriate article for it needs to be
 
           If a microprocessor is missing from the list, an appropriate article for it needs to be
 
           created and tagged with [[has feature::Crystal Well]] property.
 
           created and tagged with [[has feature::Crystal Well]] property.
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          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
 
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<table class="wikitable sortable">
 
<table class="wikitable sortable">
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<tr><th colspan="9" style="background:#D6D6FF;">Crystal Well Processors</th></tr>
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<tr><th colspan="8" style="background:#D6D6FF;">Crystal Well Processors</th></tr>
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<tr><th>Model</th><th>[[microprocessor family|Family]]</th><th>Microarchitecture</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Frequency</th><th>TDP</th><th>Process</th></tr>
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<tr><th>Model</th><th>Family</th><th>Microarchitecture</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Frequency</th><th>Process</th></tr>
 
{{#ask:
 
{{#ask:
 
     [[Category:microprocessor models by intel]]
 
     [[Category:microprocessor models by intel]]
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  |?thread count
 
  |?thread count
 
  |?base frequency
 
  |?base frequency
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|?tdp
 
 
  |?process
 
  |?process
 
  |format=template
 
  |format=template
 
  |template=proc table 1
 
  |template=proc table 1
 
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</table>
 
</table>
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== See also ==
 
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* {{intel|Iris Pro Graphics 5200}}
 
  
 
== External links ==
 
== External links ==
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[[Category:intel]]
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[[Category:Intel microarchitectures]]
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[[Category:Microarchitectures]]

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