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#REDIRECT [[intel/cores/kaby lake r]]
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{{intel title|Core i7-8600U}}
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{{mpu
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|future=Yes
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|name=Core i7-8600U
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|no image=Yes
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|designer=Intel
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|manufacturer=Intel
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|model number=i7-8600U
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|market=Mobile
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|family=Core i7
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|series=i7-8000
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|locked=Yes
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|bus type=OPI
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|bus rate=4 GT/s
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|isa=x86-64
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|isa family=x86
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|microarch=Coffee Lake
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|platform=Coffee Lake
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|core name=Coffee Lake U
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|core family=6
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|process=14 nm
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|technology=CMOS
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|word size=64 bit
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|core count=4
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|thread count=8
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|max cpus=1
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|max memory=32 GiB
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|v core min=0.55 V
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|v core max=1.52 V
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|tdp=15 W
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|tjunc min=0 °C
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|tjunc max=100 °C
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|tstorage min=-25 °C
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|tstorage max=125 °C
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}}
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'''Core i7-8600U''' is a {{arch|64}} [[quad-core]] high-end performance [[x86]] mobile microprocessor set to be introduced by [[Intel]] in late [[2017]]. This chip, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm++ process]]. The i7-8600U operates at ? GHz with a TDP of 15 W supporting a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.
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== Cache ==
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{{main|intel/microarchitectures/coffee lake#Memory_Hierarchy|l1=Coffee Lake § Cache}}
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{{cache size
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|l1 cache=256 KiB
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|l1i cache=128 KiB
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|l1i break=4x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=128 KiB
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|l1d break=4x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=1 MiB
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|l2 break=4x256 KiB
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|l2 desc=4-way set associative
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|l2 policy=write-back
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|l3 cache=8 MiB
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|l3 break=4x2 MiB
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|l3 desc=12-way set associative
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|l3 policy=write-back
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}}
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== Memory controller ==
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{{memory controller
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|type=LPDDR3-1866
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|type 2=DDR3L-1600
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|type 3=DDR4-2133
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|ecc=No
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|max mem=32 GiB
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|controllers=1
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|channels=2
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|max bandwidth=31.79 GiB/s
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|bandwidth schan=15.89 GiB/s
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|bandwidth dchan=31.79 GiB/s
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}}
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 +
== Expansions ==
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{{expansions
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| pcie revision      = 3.0
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| pcie lanes        = 12
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| pcie config        = 1x4
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| pcie config 2      = 2x2
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| pcie config 3      = 1x2+2x1
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| pcie config 4      = 4x1
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}}
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== Graphics ==
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{{empty section}}
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== Features ==
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{{x86 features
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|real=Yes
 +
|protected=Yes
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|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
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 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=Yes
 +
|fastmem=No
 +
|isrt=Yes
 +
|sba=No
 +
|mwt=Yes
 +
|sipp=Yes
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|smartmp=No
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 +
}}

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