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Difference between revisions of "intel/core i5/i5-6400t"
< intel‎ | core i5

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{{mpu
 
{{mpu
 
|name=Core i5-6400T
 
|name=Core i5-6400T
 +
|image=skylake (fclga1151).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=i5-6400T
 
|model number=i5-6400T
 
|s-spec=SR2BS
 
|s-spec=SR2BS
 +
|market=Desktop
 
|first announced=September 1, 2015
 
|first announced=September 1, 2015
 
|first launched=September 27, 2015
 
|first launched=September 27, 2015
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|turbo frequency3=2,600 MHz
 
|turbo frequency3=2,600 MHz
 
|turbo frequency4=2,500 MHz
 
|turbo frequency4=2,500 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=22
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Skylake
 
|microarch=Skylake
 +
|chipset=Sunrise Point
 
|core name=Skylake S
 
|core name=Skylake S
 
|core family=6
 
|core family=6
 +
|core model=94
 
|core stepping=R0
 
|core stepping=R0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|die area=122 mm²
 
|word size=64 bit
 
|word size=64 bit
 +
|core count=4
 +
|thread count=4
 +
|max cpus=1
 +
|max memory=64 GiB
 +
|v core min=0.55 V
 +
|v core max=1.52 V
 
|tdp=35 W
 
|tdp=35 W
 +
|tjunc min=0 °C
 +
|tjunc max=100 °C
 +
|tstorage min=-25 °C
 +
|tstorage max=125 °C
 
|package module 1={{packages/intel/fclga-1151}}
 
|package module 1={{packages/intel/fclga-1151}}
 
}}
 
}}

Revision as of 08:58, 8 July 2017

Template:mpu


Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB write-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-6400t&oldid=53224"
Facts about "Core i5-6400T - Intel"
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l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +