Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i3/6120t"
| Line 30: | Line 30: | ||
| turbo frequency4 = | | turbo frequency4 = | ||
| bus type = DMI 3.0 | | bus type = DMI 3.0 | ||
| − | | bus speed = 8 GT/s | + | | bus speed = |
| + | | bus rate = 8 GT/s | ||
| clock multiplier = | | clock multiplier = | ||
| s-spec = SR2HF | | s-spec = SR2HF | ||
Revision as of 00:42, 19 May 2016
Template:mpu
Core i3-6120T is a 64-bit dual-core low-end performance microprocessor set to be introduced by Intel in 2016.
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L1D$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L2$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
2x256 KB 4-way set associative (per core, write-back) |
| L3$ | 3 MB "MB" is not declared as a valid unit of measurement for this property. |
shared |
Expansions
Features
Facts about "Core i3-6120T - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 4-way set associative + |
| l3$ description | shared + |
