Semiconductor & Computer Engineering
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In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | ||
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== Find Chip == | == Find Chip == | ||
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}} | }} | ||
| − | == List of architectures == | + | == List of instruction set architectures == |
{{collist | {{collist | ||
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| − | * {{ | + | * {{intel|MCS-8/ISA|MCS-8 (8008)}} |
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}} | }} | ||
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* {{intel|Enhanced NetBurst|l=arch}} | * {{intel|Enhanced NetBurst|l=arch}} | ||
}} | }} | ||
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{{collist | {{collist | ||
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| style= margin-left: 20px; | | style= margin-left: 20px; | ||
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| − | '''Client | + | '''Client:''' |
* {{intel|Core (client)|l=arch}} | * {{intel|Core (client)|l=arch}} | ||
* {{intel|Penryn (client)|l=arch}} | * {{intel|Penryn (client)|l=arch}} | ||
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* {{intel|Coffee Lake|l=arch}} | * {{intel|Coffee Lake|l=arch}} | ||
* {{intel|Whiskey Lake|l=arch}} | * {{intel|Whiskey Lake|l=arch}} | ||
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* {{intel|Cannon Lake|l=arch}} ("Skymont") | * {{intel|Cannon Lake|l=arch}} ("Skymont") | ||
* {{intel|Ice Lake (client)|l=arch}} | * {{intel|Ice Lake (client)|l=arch}} | ||
| − | * {{intel| | + | * {{intel|Tigerlake|l=arch}} |
* {{intel|Alder Lake|l=arch}} | * {{intel|Alder Lake|l=arch}} | ||
* {{intel|Raptor Lake|l=arch}} | * {{intel|Raptor Lake|l=arch}} | ||
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}} | }} | ||
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{{collist | {{collist | ||
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| style= margin-left: 20px; | | style= margin-left: 20px; | ||
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| − | '''Server | + | '''Server:''' |
* {{intel|Core (server)|l=arch}} | * {{intel|Core (server)|l=arch}} | ||
* {{intel|Penryn (server)|l=arch}} | * {{intel|Penryn (server)|l=arch}} | ||
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* {{intel|Skylake (server)|l=arch}} | * {{intel|Skylake (server)|l=arch}} | ||
* {{intel|Cascade Lake|l=arch}} | * {{intel|Cascade Lake|l=arch}} | ||
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* {{intel|Ice Lake (server)|l=arch}} | * {{intel|Ice Lake (server)|l=arch}} | ||
* {{intel|Sapphire Rapids|l=arch}} | * {{intel|Sapphire Rapids|l=arch}} | ||
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}} | }} | ||
| − | + | '''ULP ([[x86]]):''' | |
{{collist | {{collist | ||
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* {{intel|Bonnell|l=arch}} | * {{intel|Bonnell|l=arch}} | ||
* {{intel|Saltwell|l=arch}} | * {{intel|Saltwell|l=arch}} | ||
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* {{intel|Goldmont|l=arch}} | * {{intel|Goldmont|l=arch}} | ||
* {{intel|Goldmont Plus|l=arch}} | * {{intel|Goldmont Plus|l=arch}} | ||
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}} | }} | ||
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'''MCU:''' | '''MCU:''' | ||
{{collist | {{collist | ||
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* {{intel|Lakemont|l=arch}} | * {{intel|Lakemont|l=arch}} | ||
}} | }} | ||
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'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
{{collist | {{collist | ||
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* Continued by [[Marvell]] .. | * Continued by [[Marvell]] .. | ||
}} | }} | ||
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'''Server (EPIC) ([[Itanium]]):''' | '''Server (EPIC) ([[Itanium]]):''' | ||
{{collist | {{collist | ||
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* {{intel|Kittson|l=arch}} | * {{intel|Kittson|l=arch}} | ||
}} | }} | ||
| − | ''' | + | '''{{intel|MIC Architectures}}:''' |
{{collist | {{collist | ||
| − | | count = | + | | count = 3 |
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* {{intel|Larrabee|l=arch}} | * {{intel|Larrabee|l=arch}} | ||
| − | + | * {{intel|Knights Ferry|l=arch}} | |
| − | + | * {{intel|Knights Corner|l=arch}} | |
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| − | * {{intel|Knights Ferry|l=arch}} | ||
| − | * {{intel|Knights Corner|l=arch}} | ||
* {{intel|Knights Landing|l=arch}} | * {{intel|Knights Landing|l=arch}} | ||
* {{intel|Knights Mill|l=arch}} | * {{intel|Knights Mill|l=arch}} | ||
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* {{intel|Knights Peak|l=arch}} | * {{intel|Knights Peak|l=arch}} | ||
}} | }} | ||
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'''GPU:''' | '''GPU:''' | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
| − | | | + | | width = 500px |
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* {{intel|Gen1|l=arch}} | * {{intel|Gen1|l=arch}} | ||
* {{intel|Gen2|l=arch}} | * {{intel|Gen2|l=arch}} | ||
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* {{intel|Gen11|l=arch}} | * {{intel|Gen11|l=arch}} | ||
* {{intel|Gen12|l=arch}} | * {{intel|Gen12|l=arch}} | ||
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}} | }} | ||
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'''Quantum:''' | '''Quantum:''' | ||
* {{intel|Surface-17}} | * {{intel|Surface-17}} | ||
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'''RAM:''' | '''RAM:''' | ||
* {{intel|3101}} | * {{intel|3101}} | ||
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* {{\\|Dynamic Tuning}} | * {{\\|Dynamic Tuning}} | ||
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* {{\\|Turbo Boost Technology}} (TBT) | * {{\\|Turbo Boost Technology}} (TBT) | ||
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}} | }} | ||
Facts about "Intel"
| company type | public + |
| founded | July 18, 1968 + |
| founded location | Mountain View, California + |
| founder | Gordon Moore +, Robert Noyce + and Andrew Grove + |
| full page name | intel + |
| headquarters | Santa Clara, California + |
| instance of | semiconductor company + |
| name | Intel + |
| website | http://www.intel.com + |
| wikidata id | Q248 + |
