Semiconductor & Computer Engineering
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In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | ||
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== Find Chip == | == Find Chip == | ||
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* {{intel|Mobile Pentium II}} | * {{intel|Mobile Pentium II}} | ||
* {{intel|Pentium}} | * {{intel|Pentium}} | ||
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* {{intel|Pentium 4}} | * {{intel|Pentium 4}} | ||
* {{intel|Pentium 4 EE}} | * {{intel|Pentium 4 EE}} | ||
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* {{intel|Pentium D}} | * {{intel|Pentium D}} | ||
* {{intel|Pentium EE}} | * {{intel|Pentium EE}} | ||
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* {{intel|Pentium II}} | * {{intel|Pentium II}} | ||
* {{intel|Pentium III}} | * {{intel|Pentium III}} | ||
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* {{intel|Pentium MMX}} | * {{intel|Pentium MMX}} | ||
* {{intel|Pentium Pro}} | * {{intel|Pentium Pro}} | ||
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* {{intel|PXA}} | * {{intel|PXA}} | ||
* {{intel|Quark}} | * {{intel|Quark}} | ||
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* {{intel|Xeon Bronze}} | * {{intel|Xeon Bronze}} | ||
* {{intel|Xeon D}} | * {{intel|Xeon D}} | ||
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* {{intel|Xeon E3}} | * {{intel|Xeon E3}} | ||
* {{intel|Xeon E5}} | * {{intel|Xeon E5}} | ||
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* {{intel|Xeon Platinum}} | * {{intel|Xeon Platinum}} | ||
* {{intel|Xeon Silver}} | * {{intel|Xeon Silver}} | ||
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}} | }} | ||
| − | == List of architectures == | + | == List of instruction set architectures == |
{{collist | {{collist | ||
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| − | * {{ | + | * {{intel|MCS-8/ISA|MCS-8 (8008)}} |
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}} | }} | ||
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* {{intel|NetBurst|l=arch}} | * {{intel|NetBurst|l=arch}} | ||
* {{intel|Enhanced NetBurst|l=arch}} | * {{intel|Enhanced NetBurst|l=arch}} | ||
| − | + | * {{intel|Core|l=arch}} | |
| − | + | * {{intel|Penryn|l=arch}} | |
| − | + | * {{intel|Nehalem|l=arch}} | |
| − | + | * {{intel|Westmere|l=arch}} | |
| − | + | * {{intel|Sandy Bridge|l=arch}} | |
| − | + | * {{intel|Ivy Bridge|l=arch}} | |
| − | + | * {{intel|Haswell|l=arch}} | |
| − | + | * {{intel|Broadwell|l=arch}} | |
| − | * {{intel|Core | + | * Skylake ({{intel|Skylake|client}}, {{intel|Skylake (server)|server}}) |
| − | * {{intel|Penryn | ||
| − | * {{intel|Nehalem | ||
| − | * {{intel|Westmere | ||
| − | * {{intel|Sandy Bridge | ||
| − | * {{intel|Ivy Bridge | ||
| − | * {{intel|Haswell | ||
| − | * {{intel|Broadwell | ||
| − | * {{intel|Skylake ( | ||
* {{intel|Kaby Lake|l=arch}} | * {{intel|Kaby Lake|l=arch}} | ||
* {{intel|Coffee Lake|l=arch}} | * {{intel|Coffee Lake|l=arch}} | ||
| − | * {{intel| | + | * {{intel|Cannonlake|l=arch}} ("Skymont") |
| − | + | * {{intel|Icelake|l=arch}} | |
| − | + | * {{intel|Tigerlake|l=arch}} | |
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| − | * {{intel| | ||
| − | * {{intel| | ||
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}} | }} | ||
| − | + | '''ULP ([[x86]]):''' | |
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{{collist | {{collist | ||
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* {{intel|Bonnell|l=arch}} | * {{intel|Bonnell|l=arch}} | ||
* {{intel|Saltwell|l=arch}} | * {{intel|Saltwell|l=arch}} | ||
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* {{intel|Goldmont|l=arch}} | * {{intel|Goldmont|l=arch}} | ||
* {{intel|Goldmont Plus|l=arch}} | * {{intel|Goldmont Plus|l=arch}} | ||
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}} | }} | ||
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'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
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* {{intel|XScale|l=arch}} | * {{intel|XScale|l=arch}} | ||
* {{intel|XScale 2|l=arch}} | * {{intel|XScale 2|l=arch}} | ||
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* Continued by [[Marvell]] .. | * Continued by [[Marvell]] .. | ||
}} | }} | ||
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'''Server (EPIC) ([[Itanium]]):''' | '''Server (EPIC) ([[Itanium]]):''' | ||
{{collist | {{collist | ||
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* {{intel|Kittson|l=arch}} | * {{intel|Kittson|l=arch}} | ||
}} | }} | ||
| − | ''' | + | '''{{intel|MIC Architectures}}:''' |
{{collist | {{collist | ||
| − | | count = | + | | count = 3 |
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* {{intel|Larrabee|l=arch}} | * {{intel|Larrabee|l=arch}} | ||
| − | + | * {{intel|Knights Ferry|l=arch}} | |
| − | + | * {{intel|Knights Corner|l=arch}} | |
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| − | * {{intel|Knights Ferry|l=arch}} | ||
| − | * {{intel|Knights Corner|l=arch}} | ||
* {{intel|Knights Landing|l=arch}} | * {{intel|Knights Landing|l=arch}} | ||
| + | * {{intel|Knights Hill|l=arch}} | ||
* {{intel|Knights Mill|l=arch}} | * {{intel|Knights Mill|l=arch}} | ||
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}} | }} | ||
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'''GPU:''' | '''GPU:''' | ||
{{collist | {{collist | ||
| count = 3 | | count = 3 | ||
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* {{intel|Gen1|l=arch}} | * {{intel|Gen1|l=arch}} | ||
* {{intel|Gen2|l=arch}} | * {{intel|Gen2|l=arch}} | ||
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* {{intel|Gen10|l=arch}} | * {{intel|Gen10|l=arch}} | ||
* {{intel|Gen11|l=arch}} | * {{intel|Gen11|l=arch}} | ||
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* {{intel|3101}} | * {{intel|3101}} | ||
* {{intel|1103}} | * {{intel|1103}} | ||
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}} | }} | ||
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{{collist | {{collist | ||
| count = 2 | | count = 2 | ||
| + | | width = 600px | ||
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| − | * {{ | + | * {{intel|Tick-Tock}} |
| − | + | * {{intel|Process-Architecture-Optimization}} (PAO) | |
| − | + | * {{intel|Turbo Boost Technology}} (TBT) | |
| − | + | * {{intel|Process Technology}} | |
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| − | * {{ | ||
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[[Category:intel]] | [[Category:intel]] | ||
Facts about "Intel"
| company type | public + |
| founded | July 18, 1968 + |
| founded location | Mountain View, California + |
| founder | Gordon Moore +, Robert Noyce + and Andrew Grove + |
| full page name | intel + |
| headquarters | Santa Clara, California + |
| instance of | semiconductor company + |
| name | Intel + |
| website | http://www.intel.com + |
| wikidata id | Q248 + |
