'''Centaur''' is a memory buffer chip designed by [[IBM]] for their {{ibm|POWER}} [[scale-up]] microprocessors. First introduced with the {{ibm|POWER8|l=arch}} microarchitecture, each Centaur chip includes 16 MiB of [[eDRAM]] and four DDR3/DDR4 [[DRAM]] ports.

Due to the inherent limitations of scaling [[DDR]] to a large number of channels, IBM uses an array of [[SerDes]] on the POWER die in order to communicate with an intermediate memory buffer chip, called '''Centaur''', which is used to access a larger set of DDR devices. Centaur is fabricated on [[22 nm]] [[SOI]], has 16 MiB of [[eDRAM]], and includes four 9 or 10B (1 byte spare) [[DRAM]] ports supporting both [[JEDEC]] [[DDR3]] and [[DDR4]]. DRAM ports are accessed in pairs, fetching 128 B [[cache lines]]/port-pair. Each port can address up to 16 logically independent DRAM ranks providing support for multiple physical [[memory ranks]].  

{{ibm|POWER8|l=arch}} and {{ibm|POWER9|l=arch}} processors that rely on Centaur communicate in a memory-channel-agnostic way. Operations such as cache-line reads/writes are sent to the chip as high-level commands. Scheduling is no longer tightly controlled by the microprocessor as it did in prior designs (e.g., {{ibm|POWER7|l=arch}}). It's worth noting that with the agnostic attribute of Centaur, new memory technologies (e.g., [[storage-class memory]]) can be introduced without any fundamental changes to the microprocessor itself.