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Latest revision | Your text | ||
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| production end = | | production end = | ||
| arch = 1-bit | | arch = 1-bit | ||
− | | isa = | + | | isa = <!-- instruction set architecture --> |
− | | word = 1 bit | + | | word = 1-bit |
| proc = <!-- process, e.g. "8 μm" --> | | proc = <!-- process, e.g. "8 μm" --> | ||
| tech = nMOS | | tech = nMOS | ||
Line 33: | Line 33: | ||
== Architecture == | == Architecture == | ||
− | The SBA family had | + | The SBA family had 8-bit instructions of two types: with immediate and without [[immediate value]]. |
− | {{ | + | * With immediate: The 5 [[MSB]]s are reserved for the address, but only up to the 30th address. The opcode is stored in the 3 LSBs. |
− | === | + | : <span style="border: 1px solid black; padding: 3px;">{{bin|00000}}-{{bin|11101}}</span><span style="border: 1px solid black; padding: 3px;">{{bin|000}}-{{bin|111}}</span> |
− | {{ | + | * Without immediate: Addresses 30 and 31 are reserved for extended instructions of 8 bits. |
− | + | : <span style="border: 1px solid black; padding: 3px;">{{bin|11110000}}-{{bin|11111111}}</span> | |
+ | |||
+ | This scheme allows for 30 addresses and 24 instructions (8 operating on [[immediate value]]s and 16 without immediates). | ||
+ | |||
+ | === Stack === | ||
+ | {{empty section}} | ||
+ | |||
+ | === Instruction Set === | ||
+ | {{isa | ||
+ | | title = SBA ISA | ||
+ | | listing = | ||
+ | {{inst|mn=ANDIN |op={{bin|AAAAA000}} |act={{l|and|In[AAAAA]|Stack[Top]}}}} | ||
+ | {{inst|mn=NANDIN |op={{bin|AAAAA001}} |act={{l|and|{{l|onot|In[AAAAA]}}|Stack[Top]}}}} | ||
+ | {{inst|mn=ANDSS |op={{bin|AAAAA010}} |act={{l|and|Store[AAAAA]|Stack[Top]}}}} | ||
+ | {{inst|mn=NANDSS |op={{bin|AAAAA011}} |act={{l|and|{{l|onot|Store[AAAAA]}}|Stack[Top]}}}} | ||
+ | {{inst|mn=ASP1 |op={{bin|AAAAA100}} |act={{l|and|Store[AAAAA]|Stack[Top]}} ; PUSH(1)}} | ||
+ | {{inst|mn=NASP1 |op={{bin|AAAAA101}} |act={{l|and|{{l|onot|Store[AAAAA]}}|Stack[Top]}} ; PUSH(1)}} | ||
+ | {{inst|mn=STORE |op={{bin|AAAAA110}} |act=Store[AAAAA] = Stack[Top] ; Stack[Top] = 1}} | ||
+ | {{inst|mn=OUTPUT |op={{bin|AAAAA111}} |act=Out[AAAAA] = Stack[Top] ; Stack[Top] = 1}} | ||
+ | {{inst|mn=RESTART |op={{bin|11110000}} |act=restarts evaluation of program}} | ||
+ | {{inst|mn=INVERT |op={{bin|11110001}} |act=Stack[Top] = {{l|onot|Stack[Top]}}}} | ||
+ | {{inst|mn=PAGE |op={{bin|11110010}} |act=Change page}} | ||
+ | {{inst|mn=HOME |op={{bin|11110011}} |act=Back to home page}} | ||
+ | {{inst|mn=PUSH0 |op={{bin|11110100}} |act=PUSH(0)}} | ||
+ | {{inst|mn=PUSH1 |op={{bin|11110101}} |act=PUSH(1)}} | ||
+ | {{inst|mn=PUSHC |op={{bin|11110110}} |act=PUSH(Stack[Top])}} | ||
+ | {{inst|mn=POP |op={{bin|11110111}} |act=POP()}} | ||
+ | {{inst|mn=AND |op={{bin|11111000}} |act=Stack[Top] = {{l|and|Stack[Top]|Stack[Top-1]}}}} | ||
+ | {{inst|mn=OR |op={{bin|11111001}} |act=Stack[Top] = {{l|or|Stack[Top]|Stack[Top-1]}}}} | ||
+ | {{inst|mn=EXOR |op={{bin|11111010}} |act=Stack[Top] = {{l|xor|Stack[Top]|Stack[Top-1]}}}} | ||
+ | {{inst|mn=COMP |op={{bin|11111011}} |act=}} | ||
+ | {{inst|mn=PAND |op={{bin|11111100}} |act={{l|and|PUSH(Stack[Top]|Stack[Top-1])}} ; Stack[Top] = 1}} | ||
+ | {{inst|mn=POR |op={{bin|11111101}} |act={{l|or|PUSH(Stack[Top]|Stack[Top-1])}} ; Stack[Top] = 1}} | ||
+ | {{inst|mn=PEXOR |op={{bin|11111110}} |act={{l|xor|PUSH(Stack[Top]|Stack[Top-1])}} ; Stack[Top] = 1}} | ||
+ | {{inst|mn=PCOMP |op={{bin|11111111}} |act=}} | ||
+ | }} | ||
{{stub}} | {{stub}} |
Facts about "SBA - General Instrument"
designer | General Instrument + |
full page name | general instrument/sba + |
instance of | microcontroller family + |
instruction set architecture | SBA + |
main designer | General Instrument + |
manufacturer | General Instrument + |
name | GIM SBA + |
package | DIP40 + |
technology | nMOS + |
word size | 1 bit (0.125 octets, 0.25 nibbles) + |