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| | {{cve title|CVE-2017-5753 (Spectre, Variant 1)}} | | {{cve title|CVE-2017-5753 (Spectre, Variant 1)}} |
| − | [[File:spectre-text.svg|200px|right]]
| + | '''CVE-2017-5753''' ('''Spectre''', '''Variant 1''', '''Bounds Check Bypass''') is a [[microprocessor]] vulnerability that allows an attacker to cause an otherwise correctly executing code to expose information to the attacker that wouldn't normally be exposed due to [[bounds checks]] being temporarily bypassed, changing the cache states of the [[microarchitecture]], thereby leaking information through [[side-channel analysis|side-channel timing analysis]]. |
| − | '''[[cve id::CVE-2017-5753]]''' ('''Spectre''', '''Variant 1''', '''Bounds Check Bypass''') is a [[microprocessor]] vulnerability that allows an attacker to cause otherwise correctly executing code to expose information to the attacker that wouldn't normally be exposed due to [[bounds checks]] being temporarily bypassed, changing the cache states of the [[microarchitecture]], thereby leaking information through [[side-channel analysis|side-channel timing analysis]]. For this attack to work, only [[speculatively execution]] is needed; the processor can still be [[in-order]]. | |
| − | | |
| − | This attack can be use on top of {{cve|CVE-2017-5715}} (Spectre, Variant 2) in order to cause a correct program to lead to this (Variant 1) vulnerability by making the microprocessor take the wrong [[branch target]].
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| | | | |
| | == Overview == | | == Overview == |
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| | This method can then be used repeatedly to read a larger part of memory. | | This method can then be used repeatedly to read a larger part of memory. |
| | | | |
| − | == Example == | + | == Mounting an attack == |
| − | Consider the following code:
| + | {{empty section}} |
| − | | |
| − | <source lang=C>
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| − | #include <stdlib.h>
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| − | | |
| − | /* a data structure */
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| − | struct array {
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| − | size_t length; /* length of data */
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| − | unsigned char val[]; /* value of data */
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| − | };
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| − | | |
| − | struct array data = { 10, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10} };
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| − | struct array data2 = /* bigger array */;
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| − | | |
| − | struct array *secrete_data = /* e.g., AES private key */;
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| − | </source>
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| − | | |
| − | In the code above there are three buffers. The first two buffers contain a series of values and a third buffer which contains secrete data for its own purpose. Now consider the following function.
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| − | | |
| − | <source lang=C>
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| − | void victim_function(size_t untrusted_caller_input) {
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| − | if (untrusted_caller_input < data.length) {
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| − | unsigned char temp = data2.val[data.val[untrusted_caller_input] * 256];
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| − | /* some more code that does something useful with `temp'. */
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| − | }
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| − | }
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| − | </source>
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| − | | |
| − | Under normal execution, if the caller calls <code>untrusted_caller_input</code> with a value [[greater than]] <code>data.length</code>, the if statement will result in <code>false</code> and the code inside the {{c|if}} block will not execute. However, consider what happens if an attacker trains the branch predictor that the if statement is going to be true. This can be done by simply calling <code>victim_function()</code> with valid inputs repeatedly. Now consider what happens if the value of <code>data.length</code> is uncached. This can also be done by reading a sufficiently large array of values.
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| − | | |
| − | When the [[branch predictor]] is trained and <code>data.length</code> is uncached and a shared array <code>data2.val</code> is also uncached, an attacker can call <code>victim_function</code> with a more malicious input such as the value of <code>secrete_data - data</code>. When this is done, the microprocessor will issue a [[cache miss]] and request to get the value of <code>data.length</code> from memory. Meanwhile the processor will mispredict the path since we trained it to assume the if statement is most likely going to be true. Meanwhile there will be a substantial delay until the value as a result of the [[cache miss]] is brought back from [[DRAM]]. During this time, the processor will [[speculative execution|speculatively]] execute <code>data2.val[data.val[untrusted_caller_input] * 256]</code>.
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| − | | |
| − | Since the attacker called <code>untrusted_caller_input</code> with the value of <code>secrete_data - data</code> which is out of bound, the speculative execution logic will then use <code>secrete_data[0]</code> to compute the address of <code>data2.val[secrete_data[0] * 256]</code>. Since <code>data2.val</code> is uncached, the microprocessor will issue another cache miss for that address and go and grab that value from memory.
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| − | | |
| − | When this happens, the value of <code>data.length</code> will come back and the processor will realize that it has [[branch misprediction|mispredicted]]. The processor will then rewind the state of the machine back and start executing at the correct path (where the if statement is false).
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| − | | |
| − | Although the architectural state of the machine has been restored, some microarchitectural states have changed. In particular, the value of <code>data2.val[secrete_data[0] * 256]</code> which resulted in a [[cache miss]] will come back. Since the rest of the values of <code>data2.val</code> are not cached, the attacker can now use [[side-channel analysis]] to infer the values of <code>secrete_data</code>.
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| − | | |
| − | For example, suppose <code>secrete_data</code> was initialized as followed:
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| − | | |
| − | <source lang=C>
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| − | struct array *secrete_data = { 8, { 'S', 'e', 'c', 'r', 'e', 't', 'e', '\0'};
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| − | </source>
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| − | | |
| − | If the attacker is trying to infer the value of the first byte, we will feed <code>untrusted_caller_input</code> the correct offset which will result in <code>data2.val[secrete_data[0] * 256]</code> being executed which in term will cause <code>data2.val['S' * 256]</code> or <code>data2.val[21248]</code> to be loaded into the cache from [[main memory]]. Using a [[side-channel analysis]] timing attack, the attacker will attempt to read from <code>data2.val[X * 256]</code> various values. Since only <code>data2.val[secrete_data[0] * 256]</code> is cached, reading any other value will result in a cache miss which will take some time for the processor to bring the value back from memory. By analysing which index was instant (i.e. did not result in a cache miss), the attacker can infer the value of <code>secrete_data[0]</code>.
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| − | | |
| − | The attacker can then continue to do this whole procedure repeatedly to get the value of <code>secrete_data[1]</code>, then <code>secrete_data[2]</code>, etc until the entire content of the secrete data is indirectly leaked to the attacker.
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| − | | |
| − | === Breaking sandbox isolation ===
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| − | Since the attack makes use of the very fundamental behavior of a modern microprocessor, it can be taken advantage in a more restrictive environment such as a [[sandbox]] (e.g., a [[browser]]). A specially constructed piece of [[JavaScript]] can running on a browser that has a [[JIT]] compiler can be used to leak the entire memory of its parent process (i.e. the browser, other tabs, and any other stored shared memory) using this method. This aspect of the vulnerability is particularly dangerous since [[JavaScript]] can be sent to an innocent web client via something as simple as an ad.
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| − | | |
| − | ==== JavaScript ====
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| − | The paper describing the attack (see [[#References]]) listed the following JavaScript snippet.
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| − | | |
| − | <source lang=JavaScript>
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| − | if (index < simpleByteArray.length) {
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| − | index = simpleByteArray[index | 0];
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| − | index = (((index * TABLE1_STRIDE)|0) & (TABLE1_BYTES-1))|0;
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| − | localJunk ^= probeTable[index|0]|0;
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| − | }
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| − | </source>
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| − | | |
| − | The cache status of <code>probeTable[byte * TABLE1_STRIDE]</code> can then be used by an attacker to [[side-channel analysis|infer the value]] of a given memory location.
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| − | | |
| − | == Affected Processors ==
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| − | Below is a list of known affected processors, alphabetized. This is '''NOT''' en exhaustive list but rather the once we were able to verify!
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| − | | |
| − | {| class="wikitable"
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| − | |-
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| − | ! colspan="3" | List of Processors affected by Spectre, Variant 1
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| − | |-
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| − | ! Designer !! Processor/Architecture !! Related Notes
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| − | |-
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| − | | rowspan="6" | [[Apple]] || {{apple|Swift|l=arch}} ({{apple|A6}}/{{apple|A6X}}) || rowspan="6" | [https://support.apple.com/en-us/HT201222 Post]<br>[https://support.apple.com/en-us/HT208331 Post]
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| − | |-
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| − | | {{apple|Cyclone|l=arch}} ({{apple|A7}})
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| − | |-
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| − | | {{apple|Typhoon|l=arch}} ({{apple|A8}}/{{apple|A8X}})
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| − | |-
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| − | | {{apple|Twister|l=arch}} ({{apple|A9}}/{{apple|A9X}})
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| − | |-
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| − | | {{apple|Hurricane|l=arch}} ({{apple|A10}}/{{apple|A10X}})
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| − | |-
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| − | | {{apple|Monsoon|l=arch}} ({{apple|A11}}/{{apple|A11X}})
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| − | |-
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| − | | rowspan="5"| [[AMD]] || {{amd|Bulldozer|l=arch}} || rowspan="5" | [https://www.amd.com/en/corporate/speculative-execution Post]
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| − | |-
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| − | | {{amd|Piledriver|l=arch}}
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| − | |-
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| − | | {{amd|Steamroller|l=arch}}
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| − | |-
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| − | | {{amd|Excavator|l=arch}}
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| − | |-
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| − | | {{amd|Zen|l=arch}}
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| − | |-
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| − | | rowspan="10" | [[ARM Holdings|ARM]] || {{armh|Cortex-R7|l=arch}} || rowspan="10" | [https://developer.arm.com/support/security-update Post]
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| − | |-
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| − | | {{armh|Cortex-R8|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A8|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A9|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A15|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A17|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A57|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A72|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A73|l=arch}}
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| − | |-
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| − | | {{armh|Cortex-A75|l=arch}}
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| − | |-
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| − | | rowspan="3" | [[Fujitsu]] || [[SPARC64 X+]] || rowspan="3" | [http://support.ts.fujitsu.com/content/SideChannelAnalysisMethod.asp Post]
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| − | |-
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| − | | [[SPARC64 XIfx]]
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| − | |-
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| − | | [[SPARC64 XII]]
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| − | |-
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| − | | rowspan="10" | [[IBM]] || {{ibm|PowerPC 970}}
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| − | |-
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| − | | {{ibm|POWER6|l=arch}}
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| − | |-
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| − | | {{ibm|POWER7|l=arch}} || rowspan="5" | [https://www.ibm.com/blogs/psirt/potential-impact-processors-power-family/ Post]<br>[http://www-01.ibm.com/support/docview.wss?uid=isg3T1026811 Security Bulletin]
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| − | |-
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| − | | {{ibm|POWER7+|l=arch}}
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| − | |-
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| − | | {{ibm|POWER8|l=arch}}
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| − | |-
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| − | | {{ibm|POWER8+|l=arch}}
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| − | |-
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| − | | {{ibm|POWER9|l=arch}}
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| − | |-
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| − | | {{ibm|z12|l=arch}} || rowspan="3" |
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| − | |-
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| − | | {{ibm|z13|l=arch}}
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| − | |-
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| − | | {{ibm|z14|l=arch}}
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| − | |-
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| − | | rowspan="13" | [[Intel]] || {{intel|Nehalem|l=arch}} || rowspan="2" |
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| − | |-
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| − | | {{intel|Westmere|l=arch}}
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| − | |-
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| − | |{{intel|Sandy Bridge|l=arch}} || rowspan="11" | [https://security-center.intel.com/advisory.aspx?intelid=INTEL-SA-00088&languageid=en-fr Post]
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| − | |-
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| − | | {{intel|Ivy Bridge|l=arch}}
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| − | |-
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| − | | {{intel|Haswell|l=arch}}
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| − | |-
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| − | | {{intel|Broadwell|l=arch}}
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| − | |-
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| − | | {{intel|Skylake|l=arch}}
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| − | |-
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| − | | {{intel|Kaby Lake|l=arch}}
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| − | |-
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| − | | {{intel|Coffee Lake|l=arch}}
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| − | |-
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| − | | {{intel|Silvermont|l=arch}}
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| − | |-
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| − | | {{intel|Airmont|l=arch}}
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| − | |-
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| − | | {{intel|Goldmont|l=arch}}
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| − | |-
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| − | | {{intel|Goldmont Plus|l=arch}}
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| − | |-
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| − | | rowspan="2" | {{mipstech|-|MIPS}} || {{mipstech|P5600}} || rowspan="2" | [https://www.mips.com/blog/mips-response-on-speculative-execution-and-side-channel-vulnerabilities/ Post]
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| − | |-
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| − | | {{mipstech|P6600}}
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| − | |-
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| − | | [[Motorola]] || {{motorola|PowerPC 74xx}} || rowspan="3" | [https://tenfourfox.blogspot.co.at/2018/01/actual-field-testing-of-spectre-on.html Post]
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| − | |}
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| − | {{expand list}}
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| − | | |
| − | == See also ==
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| − | * {{cve|CVE-2017-5715}}, Spectre, Variant 2
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| − | * {{cve|CVE-2017-5754}}, Meltdown, Variant 3
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| − | | |
| − | == References ==
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| − | * Kocher, Paul, et al. "[https://arxiv.org/abs/1801.01203 Spectre Attacks: Exploiting Speculative Execution]." arXiv preprint arXiv:1801.01203 (2018).
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| − | * "CVE-2017-5753", https://www.cve.mitre.org/cgi-bin/cvename.cgi?name=2017-5753
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| − | | |
| − | == Documents ==
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| − | * [[:File:intel-ref-336983-001.pdf|White Paper: Intel Analysis of Speculative Execution Side Channels]]
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| | [[category:cve]] | | [[category:cve]] |
