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====Domino Logic==== | ====Domino Logic==== | ||
{{main|cmos/domino|l1=Domino Logic|cmos/multiple-output domino logic|l2=Multiple-Output Domino Logic (MODL)}} | {{main|cmos/domino|l1=Domino Logic|cmos/multiple-output domino logic|l2=Multiple-Output Domino Logic (MODL)}} | ||
− | Domino logic solves the monotonicity problem in dynamic gates by placing | + | Domino logic solves the monotonicity problem in dynamic gates by placing a static CMOS inverter between cascading dynamic gates. The use of the inverter converts the monotonically falling output node into a rising one which is suitable for the next gate. The name '''domino gate''' is given to this dynamic-static CMOS pair because of its resemblance the behavior of domino tiles - all the gates are precharged simultaneously whereas the evaluation phase occurs sequentially. |
====Dual-rail Domino Logic==== | ====Dual-rail Domino Logic==== | ||
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{{empty section}} | {{empty section}} | ||
− | ===Pass-Transistor Logic=== | + | ===Pass-Transistor Logic (PTL)=== |
{{main|cmos/pass-transistor|l1=Pass-Transistor Logic}} | {{main|cmos/pass-transistor|l1=Pass-Transistor Logic}} | ||
In Pass-Transistor Logic (PTL), inputs drive both gate terminals and source/drain terminals. In specialized circumstances, PTL can be significantly improve the speed, power, and area of the logic. In general, PTL usually yields equivalent logic to static CMOS - especially those making heavy use of [[transmission gate]]s. PTL is not regenerative degrading the output as you chain them. | In Pass-Transistor Logic (PTL), inputs drive both gate terminals and source/drain terminals. In specialized circumstances, PTL can be significantly improve the speed, power, and area of the logic. In general, PTL usually yields equivalent logic to static CMOS - especially those making heavy use of [[transmission gate]]s. PTL is not regenerative degrading the output as you chain them. | ||
− | ==== Complementary Pass-Transistor Logic==== | + | ==== Complementary Pass-Transistor Logic (CPTL)==== |
{{main|cmos/complementary pass-transistor|l1=Complementary Pass-Transistor Logic}} | {{main|cmos/complementary pass-transistor|l1=Complementary Pass-Transistor Logic}} | ||
Complementary Pass-Transistor Logic (CPTL) is a more specialized version of Pass-Transistor Logic which makes use of both the inputs and their complements. Likewise both the output and its complement gets generated. | Complementary Pass-Transistor Logic (CPTL) is a more specialized version of Pass-Transistor Logic which makes use of both the inputs and their complements. Likewise both the output and its complement gets generated. | ||
− | ==== Lean Integration with Pass Transistors ==== | + | ==== Lean Integration with Pass Transistors (LEAP) ==== |
{{main|cmos/lean integration with pass transistors|l1=Lean Integration with Pass Transistors}} | {{main|cmos/lean integration with pass transistors|l1=Lean Integration with Pass Transistors}} | ||
{{empty section}} | {{empty section}} | ||
− | === Cascade Voltage Switch Logic === | + | === Cascade Voltage Switch Logic (CVSL) === |
{{main|cmos/cascade voltage switch logic|l1=Cascade Voltage Switch Logic (CVSL)}} | {{main|cmos/cascade voltage switch logic|l1=Cascade Voltage Switch Logic (CVSL)}} | ||
{{empty section}} | {{empty section}} |