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{{cavium title|CN3860-500 EXP}} | {{cavium title|CN3860-500 EXP}} | ||
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| name = Cavium CN3860-500 EXP | | name = Cavium CN3860-500 EXP | ||
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| model number = CN3860-500 EXP | | model number = CN3860-500 EXP | ||
| part number = CN3860-500BG1521-EXP | | part number = CN3860-500BG1521-EXP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
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| market = Networking | | market = Networking | ||
| − | | first announced = | + | | first announced = August 22, 2005 |
| − | | first launched = | + | | first launched = August 22, 2005 |
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The '''CN3860-500 EXP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | The '''CN3860-500 EXP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | ||
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| + | == Block diagram == | ||
| + | [[File:octeon cn38xx block diagram.png|750px]] | ||
| + | |||
| + | == Datasheet == | ||
| + | * [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX/CN36XX 4 to 16-Core Product Brief]] | ||
Latest revision as of 16:11, 13 December 2017
| Edit Values | |||||||
| Cavium CN3860-500 EXP | |||||||
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| General Info | |||||||
| Designer | Cavium | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | CN3860-500 EXP | ||||||
| Part Number | CN3860-500BG1521-EXP | ||||||
| Market | Networking | ||||||
| Introduction | August 22, 2005 (announced) August 22, 2005 (launched) | ||||||
| General Specs | |||||||
| Family | OCTEON | ||||||
| Series | CN3800 | ||||||
| Frequency | 500 MHz | ||||||
| Microarchitecture | |||||||
| ISA | MIPS64 (MIPS) | ||||||
| Microarchitecture | cnMIPS | ||||||
| Core Name | cnMIPS | ||||||
| Process | 130 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 16 | ||||||
| Threads | 16 | ||||||
| Max Memory | 16 GiB | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Packaging | |||||||
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The CN3860-500 EXP is a 64-bit hexadeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3860-500 EXP - Cavium"
| has ecc memory support | true + |
| has hardware accelerators for data compression | true + |
| has hardware accelerators for data decompression | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for regular expression | true + |
| has hardware accelerators for tcp packet processing | true + |
| l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 64-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR2-800 + |
