Semiconductor & Computer Engineering
From WikiChip
Information for "cavium/octeon/cn3830-500bg1521-exp"
Basic information
| Display title | CN3830-500 EXP - Cavium |
| Default sort key | CN3830-500 EXP, Cavium |
| Page length (in bytes) | 3,729 |
| Page ID | 12118 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 6 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | ChipIt (talk | contribs) |
| Date of page creation | 18:16, 10 December 2016 |
| Latest editor | ChippyBot (talk | contribs) |
| Date of latest edit | 15:11, 13 December 2017 |
| Total number of edits | 8 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (16) | Templates used on this page:
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Facts about "CN3830-500 EXP - Cavium"
| has ecc memory support | true + |
| has hardware accelerators for data compression | true + |
| has hardware accelerators for data decompression | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for regular expression | true + |
| has hardware accelerators for tcp packet processing | true + |
| l1$ size | 160 KiB (163,840 B, 0.156 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 64-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR2-800 + |